clk: renesas: rcar-gen4: Use defines for common CPG registers

Add symbolic definitions for common CPG registers.
Replace hardcoded register offsets by the new definitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8ae48a5dac59cb5723fbca3842b93a9e51ffe1ca.1721648548.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index d75d01b4c554a9e094540acc99eae27cf57bee69..14042d6dc4dd3e21c704e6377de6b51fabe7a60d 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -116,17 +116,17 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        DEF_FIXED("cp",         R8A779A0_CLK_CP,        CLK_EXTAL,      2, 1),
        DEF_FIXED("cl16mck",    R8A779A0_CLK_CL16MCK,   CLK_PLL1_DIV2,  64, 1),
 
-       DEF_GEN4_SDH("sd0h",    R8A779A0_CLK_SD0H,      CLK_SDSRC,         0x870),
-       DEF_GEN4_SD("sd0",      R8A779A0_CLK_SD0,       R8A779A0_CLK_SD0H, 0x870),
+       DEF_GEN4_SDH("sd0h",    R8A779A0_CLK_SD0H,      CLK_SDSRC,         CPG_SD0CKCR),
+       DEF_GEN4_SD("sd0",      R8A779A0_CLK_SD0,       R8A779A0_CLK_SD0H, CPG_SD0CKCR),
 
        DEF_BASE("rpc",         R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
        DEF_BASE("rpcd2",       R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
                 R8A779A0_CLK_RPC),
 
-       DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
-       DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
-       DEF_DIV6P1("csi0",      R8A779A0_CLK_CSI0,      CLK_PLL5_DIV4,  0x880),
-       DEF_DIV6P1("dsi",       R8A779A0_CLK_DSI,       CLK_PLL5_DIV4,  0x884),
+       DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,       CLK_PLL5_DIV4,  CPG_MSOCKCR),
+       DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,     CLK_PLL5_DIV4,  CPG_CANFDCKCR),
+       DEF_DIV6P1("csi0",      R8A779A0_CLK_CSI0,      CLK_PLL5_DIV4,  CPG_CSICKCR),
+       DEF_DIV6P1("dsi",       R8A779A0_CLK_DSI,       CLK_PLL5_DIV4,  CPG_DSIEXTCKCR),
 
        DEF_GEN4_OSC("osc",     R8A779A0_CLK_OSC,       CLK_EXTAL,      8),
        DEF_GEN4_MDSEL("r",     R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 0a14f34105d0fadd0d7bcf85bc42b0e278fc46a5..832ba0bacdf02346861e08e683b21504385ac267 100644 (file)
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -115,13 +115,13 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
        DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
        DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
 
-       DEF_GEN4_SDH("sd0h",    R8A779F0_CLK_SD0H,      CLK_SDSRC,         0x870),
-       DEF_GEN4_SD("sd0",      R8A779F0_CLK_SD0,       R8A779F0_CLK_SD0H, 0x870),
+       DEF_GEN4_SDH("sd0h",    R8A779F0_CLK_SD0H,      CLK_SDSRC,         CPG_SD0CKCR),
+       DEF_GEN4_SD("sd0",      R8A779F0_CLK_SD0,       R8A779F0_CLK_SD0H, CPG_SD0CKCR),
 
        DEF_BASE("rpc",         R8A779F0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
        DEF_BASE("rpcd2",       R8A779F0_CLK_RPCD2,     CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
 
-       DEF_DIV6P1("mso",       R8A779F0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
+       DEF_DIV6P1("mso",       R8A779F0_CLK_MSO,       CLK_PLL5_DIV4,  CPG_MSOCKCR),
 
        DEF_GEN4_OSC("osc",     R8A779F0_CLK_OSC,       CLK_EXTAL,      8),
        DEF_GEN4_MDSEL("r",     R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index a2bc3b0d38db6570c3f1ec85834140e9fd62dbe8..fb67e8724eeb62351d61bfd8fc414122ab69f82b 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -146,14 +146,14 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        DEF_FIXED("viobusd2",   R8A779G0_CLK_VIOBUSD2,  CLK_VIO,        2, 1),
        DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
        DEF_FIXED("vcbusd2",    R8A779G0_CLK_VCBUSD2,   CLK_VC,         2, 1),
-       DEF_DIV6P1("canfd",     R8A779G0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
-       DEF_DIV6P1("csi",       R8A779G0_CLK_CSI,       CLK_PLL5_DIV4,  0x880),
+       DEF_DIV6P1("canfd",     R8A779G0_CLK_CANFD,     CLK_PLL5_DIV4,  CPG_CANFDCKCR),
+       DEF_DIV6P1("csi",       R8A779G0_CLK_CSI,       CLK_PLL5_DIV4,  CPG_CSICKCR),
        DEF_FIXED("dsiref",     R8A779G0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
-       DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  0x884),
+       DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  CPG_DSIEXTCKCR),
 
-       DEF_GEN4_SDH("sd0h",    R8A779G0_CLK_SD0H,      CLK_SDSRC,         0x870),
-       DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       R8A779G0_CLK_SD0H, 0x870),
-       DEF_DIV6P1("mso",       R8A779G0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
+       DEF_GEN4_SDH("sd0h",    R8A779G0_CLK_SD0H,      CLK_SDSRC,         CPG_SD0CKCR),
+       DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       R8A779G0_CLK_SD0H, CPG_SD0CKCR),
+       DEF_DIV6P1("mso",       R8A779G0_CLK_MSO,       CLK_PLL5_DIV4,  CPG_MSOCKCR),
 
        DEF_BASE("rpc",         R8A779G0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
        DEF_BASE("rpcd2",       R8A779G0_CLK_RPCD2,     CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),

diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 0fe7c8168fb391dfc37f824d7f6c9dcb397494e5..adfdbf768dc31ec4d1d3a5099d7d9f6cd1c86781 100644 (file)
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -156,14 +156,14 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = {
        DEF_FIXED("viobusd2",   R8A779H0_CLK_VIOBUSD2,  CLK_VIOSRC,     2, 1),
        DEF_FIXED("vcbusd1",    R8A779H0_CLK_VCBUSD1,   CLK_VCSRC,      1, 1),
        DEF_FIXED("vcbusd2",    R8A779H0_CLK_VCBUSD2,   CLK_VCSRC,      2, 1),
-       DEF_DIV6P1("canfd",     R8A779H0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
-       DEF_DIV6P1("csi",       R8A779H0_CLK_CSI,       CLK_PLL5_DIV4,  0x880),
+       DEF_DIV6P1("canfd",     R8A779H0_CLK_CANFD,     CLK_PLL5_DIV4,  CPG_CANFDCKCR),
+       DEF_DIV6P1("csi",       R8A779H0_CLK_CSI,       CLK_PLL5_DIV4,  CPG_CSICKCR),
        DEF_FIXED("dsiref",     R8A779H0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
-       DEF_DIV6P1("dsiext",    R8A779H0_CLK_DSIEXT,    CLK_PLL5_DIV4,  0x884),
-       DEF_DIV6P1("mso",       R8A779H0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
+       DEF_DIV6P1("dsiext",    R8A779H0_CLK_DSIEXT,    CLK_PLL5_DIV4,  CPG_DSIEXTCKCR),
+       DEF_DIV6P1("mso",       R8A779H0_CLK_MSO,       CLK_PLL5_DIV4,  CPG_MSOCKCR),
 
-       DEF_GEN4_SDH("sd0h",    R8A779H0_CLK_SD0H,      CLK_SDSRC,         0x870),
-       DEF_GEN4_SD("sd0",      R8A779H0_CLK_SD0,       R8A779H0_CLK_SD0H, 0x870),
+       DEF_GEN4_SDH("sd0h",    R8A779H0_CLK_SD0H,      CLK_SDSRC,         CPG_SD0CKCR),
+       DEF_GEN4_SD("sd0",      R8A779H0_CLK_SD0,       R8A779H0_CLK_SD0H, CPG_SD0CKCR),
 
        DEF_BASE("rpc",         R8A779H0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
        DEF_BASE("rpcd2",       R8A779H0_CLK_RPCD2,     CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC),

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index d0329ac84730d681d0b2741479acf8a27adbe076..a277cf0598c4e6670a1d49ffd38ede21a874282a 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -67,6 +67,12 @@ struct rcar_gen4_cpg_pll_config {
        u8 osc_prediv;
 };
 
+#define CPG_SD0CKCR    0x870   /* SD-IF0 Clock Frequency Control Register */
+#define CPG_CANFDCKCR  0x878   /* CAN-FD Clock Frequency Control Register */
+#define CPG_MSOCKCR    0x87c   /* MSIOF Clock Frequency Control Register */
+#define CPG_CSICKCR    0x880   /* CSI Clock Frequency Control Register */
+#define CPG_DSIEXTCKCR 0x884   /* DSI Clock Frequency Control Register */
+
 struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
        const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
        struct clk **clks, void __iomem *base,