drm/i915: Rename PIPECONF refresh select bits

Rename the PIPECONF refresh rate select bits to be
less cryptic. Also nothing eDP specific about these as they
also select between FP0 vs. FP1 for the DPLL and thus can be
used to change the refresh rate on other output types as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220310004802.16310-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 3979ceaaf6510ec05ed9dab58f56c4c10914cd63..c97b5dee8cae6f098dcd8489c3ca966bdaa73e4c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -111,9 +111,9 @@ intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
        u32 val, bit;
 
        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-               bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+               bit = PIPECONF_REFRESH_RATE_ALT_VLV;
        else
-               bit = PIPECONF_EDP_RR_MODE_SWITCH;
+               bit = PIPECONF_REFRESH_RATE_ALT_ILK;
 
        val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92a90a54c3e4f6e859b45b02aa533b7cf12a826b..56042d363a15221193081d8f8f76fc026b3c7acf 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3701,11 +3701,11 @@
 #define   PIPECONF_INTERLACE_IF_ID_ILK         REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
 #define   PIPECONF_INTERLACE_IF_ID_DBL_ILK     REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
 #define   PIPECONF_INTERLACE_PF_ID_DBL_ILK     REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
-#define   PIPECONF_EDP_RR_MODE_SWITCH          REG_BIT(20)
+#define   PIPECONF_REFRESH_RATE_ALT_ILK                REG_BIT(20)
 #define   PIPECONF_MSA_TIMING_DELAY_MASK       REG_GENMASK(19, 18) /* ilk/snb/ivb */
 #define   PIPECONF_MSA_TIMING_DELAY(x)         REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x))
 #define   PIPECONF_CXSR_DOWNCLOCK              REG_BIT(16)
-#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV      REG_BIT(14)
+#define   PIPECONF_REFRESH_RATE_ALT_VLV                REG_BIT(14)
 #define   PIPECONF_COLOR_RANGE_SELECT          REG_BIT(13)
 #define   PIPECONF_OUTPUT_COLORSPACE_MASK      REG_GENMASK(12, 11) /* ilk-ivb */
 #define   PIPECONF_OUTPUT_COLORSPACE_RGB       REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */