drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR2_MAN_TRK_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/72934c8ac3a923ca0c12fc6cdeec1e0b87ecc4a4.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 0412a2e1d638353a8cb100d3d5471de5f5a1f6bd..638f01f0c328e3612b44994a2eb2d5d3ff4193f6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -844,7 +844,8 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-       intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+       intel_de_rmw(dev_priv,
+                    PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder),
                     0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
 
        intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
@@ -919,10 +920,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
        if (intel_dp->psr.psr2_sel_fetch_enabled) {
                u32 tmp;
 
-               tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
+               tmp = intel_de_read(dev_priv,
+                                   PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder));
                drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
        } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
-               intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), 0);
+               intel_de_write(dev_priv,
+                              PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0);
        }
 
        if (psr2_su_region_et_valid(intel_dp))
@@ -1681,7 +1684,8 @@ void intel_psr_get_config(struct intel_encoder *encoder,
                goto unlock;
 
        if (HAS_PSR2_SEL_FETCH(dev_priv)) {
-               val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
+               val = intel_de_read(dev_priv,
+                                   PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder));
                if (val & PSR2_MAN_TRK_CTL_ENABLE)
                        pipe_config->enable_psr2_sel_fetch = true;
        }
@@ -2251,7 +2255,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
 
        if (intel_dp->psr.psr2_sel_fetch_enabled)
                intel_de_write(dev_priv,
-                              PSR2_MAN_TRK_CTL(cpu_transcoder),
+                              PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
                               man_trk_ctl_enable_bit_get(dev_priv) |
                               man_trk_ctl_partial_frame_bit_get(dev_priv) |
                               man_trk_ctl_single_full_frame_bit_get(dev_priv) |
@@ -2293,7 +2297,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
                break;
        }
 
-       intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
+       intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
                       crtc_state->psr2_man_track_ctl);
 
        if (!crtc_state->enable_psr2_su_region_et)
@@ -3014,7 +3018,9 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
                val = man_trk_ctl_enable_bit_get(dev_priv) |
                      man_trk_ctl_partial_frame_bit_get(dev_priv) |
                      man_trk_ctl_continuos_full_frame(dev_priv);
-               intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), val);
+               intel_de_write(dev_priv,
+                              PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
+                              val);
                intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
                intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
        } else {
@@ -3112,7 +3118,8 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
                                 * SU configuration in case update is sent for any reason after
                                 * sff bit gets cleared by the HW on next vblank.
                                 */
-                               intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
+                               intel_de_write(dev_priv,
+                                              PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
                                               val);
                                intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
                                intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 5504593aa9d0fcef688eae992f49ed3320a8aa9b..db990f30f0d550430e213158ef7694040e6e67b6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -229,7 +229,7 @@
 
 #define _PSR2_MAN_TRK_CTL_A                                    0x60910
 #define _PSR2_MAN_TRK_CTL_EDP                                  0x6f910
-#define PSR2_MAN_TRK_CTL(tran)                                 _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)
+#define PSR2_MAN_TRK_CTL(dev_priv, tran)                                       _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)
 #define  PSR2_MAN_TRK_CTL_ENABLE                               REG_BIT(31)
 #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK            REG_GENMASK(30, 21)
 #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)            REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)