if (IS_ERR(cdclk_state))
                return PTR_ERR(cdclk_state);
 
-       cdclk_state->force_min_cdclk_changed = true;
        cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
 
-       ret = intel_atomic_lock_global_state(&cdclk_state->base);
-       if (ret)
-               return ret;
-
        return drm_atomic_commit(&state->base);
 }
 
 
        if (!cdclk_state)
                return NULL;
 
-       cdclk_state->force_min_cdclk_changed = false;
        cdclk_state->pipe = INVALID_PIPE;
 
        return &cdclk_state->base;
                if (ret)
                        return ret;
        } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
+                  old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
                   intel_cdclk_changed(&old_cdclk_state->logical,
                                       &new_cdclk_state->logical)) {
                ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
 
 
        /* forced minimum cdclk for glk+ audio w/a */
        int force_min_cdclk;
-       bool force_min_cdclk_changed;
 
        /* bitmask of active pipes */
        u8 active_pipes;
 
                                    bool *need_cdclk_calc)
 {
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-       struct intel_cdclk_state *new_cdclk_state;
+       const struct intel_cdclk_state *old_cdclk_state;
+       const struct intel_cdclk_state *new_cdclk_state;
        struct intel_plane_state *plane_state;
        struct intel_bw_state *new_bw_state;
        struct intel_plane *plane;
                        return ret;
        }
 
+       old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
        new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
 
-       if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
+       if (new_cdclk_state &&
+           old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
                *need_cdclk_calc = true;
 
        ret = dev_priv->display.bw_calc_min_cdclk(state);