u16 ctrl, total;
        struct pci_sriov *iov;
        struct resource *res;
+       const char *res_name;
        struct pci_dev *pdev;
 
        pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
        nres = 0;
        for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
                res = &dev->resource[i + PCI_IOV_RESOURCES];
+               res_name = pci_resource_name(dev, i + PCI_IOV_RESOURCES);
+
                /*
                 * If it is already FIXED, don't change it, something
                 * (perhaps EA or header fixups) wants it this way.
                }
                iov->barsz[i] = resource_size(res);
                res->end = res->start + resource_size(res) * total - 1;
-               pci_info(dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n",
-                        i, res, i, total);
+               pci_info(dev, "%s %pR: contains BAR %d for %d VFs\n",
+                        res_name, res, i, total);
                i += bar64;
                nres++;
        }
 
 static int pci_ea_read(struct pci_dev *dev, int offset)
 {
        struct resource *res;
+       const char *res_name;
        int ent_size, ent_offset = offset;
        resource_size_t start, end;
        unsigned long flags;
                goto out;
 
        res = pci_ea_get_resource(dev, bei, prop);
+       res_name = pci_resource_name(dev, bei);
        if (!res) {
                pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
                goto out;
        res->flags = flags;
 
        if (bei <= PCI_EA_BEI_BAR5)
-               pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
-                          bei, res, prop);
+               pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
+                        res_name, res, prop);
        else if (bei == PCI_EA_BEI_ROM)
-               pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
-                          res, prop);
+               pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
+                        res_name, res, prop);
        else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
-               pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
-                          bei - PCI_EA_BEI_VF_BAR0, res, prop);
+               pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
+                        res_name, res, prop);
        else
-               pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
+               pci_info(dev, "BEI %d %pR: from Enhanced Allocation, properties %#02x\n",
                           bei, res, prop);
 
 out:
                                           resource_size_t align, bool resize)
 {
        struct resource *r = &dev->resource[bar];
+       const char *r_name = pci_resource_name(dev, bar);
        resource_size_t size;
 
        if (!(r->flags & IORESOURCE_MEM))
                return;
 
        if (r->flags & IORESOURCE_PCI_FIXED) {
-               pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
-                        bar, r, (unsigned long long)align);
+               pci_info(dev, "%s %pR: ignoring requested alignment %#llx\n",
+                        r_name, r, (unsigned long long)align);
                return;
        }
 
         * devices and we use the second.
         */
 
-       pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
-                bar, r, (unsigned long long)align);
+       pci_info(dev, "%s %pR: requesting alignment to %#llx\n",
+                r_name, r, (unsigned long long)align);
 
        if (resize) {
                r->start = 0;
 
        u64 l64, sz64, mask64;
        u16 orig_cmd;
        struct pci_bus_region region, inverted_region;
+       const char *res_name = pci_resource_name(dev, res - dev->resource);
 
        mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
 
 
        sz64 = pci_size(l64, sz64, mask64);
        if (!sz64) {
-               pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
-                        pos);
+               pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name);
                goto fail;
        }
 
                        res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
                        res->start = 0;
                        res->end = 0;
-                       pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
-                               pos, (unsigned long long)sz64);
+                       pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n",
+                               res_name, (unsigned long long)sz64);
                        goto out;
                }
 
                        res->flags |= IORESOURCE_UNSET;
                        res->start = 0;
                        res->end = sz64 - 1;
-                       pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
-                                pos, (unsigned long long)l64);
+                       pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n",
+                                res_name, (unsigned long long)l64);
                        goto out;
                }
        }
                res->flags |= IORESOURCE_UNSET;
                res->start = 0;
                res->end = region.end - region.start;
-               pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
-                        pos, (unsigned long long)region.start);
+               pci_info(dev, "%s: initial BAR value %#010llx invalid\n",
+                        res_name, (unsigned long long)region.start);
        }
 
        goto out;
        res->flags = 0;
 out:
        if (res->flags)
-               pci_info(dev, "reg 0x%x: %pR\n", pos, res);
+               pci_info(dev, "%s %pR\n", res_name, res);
 
        return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
 }
                                res = &dev->resource[0];
                                res->flags = LEGACY_IO_RESOURCE;
                                pcibios_bus_to_resource(dev->bus, res, ®ion);
-                               pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
+                               pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n",
                                         res);
                                region.start = 0x3F6;
                                region.end = 0x3F6;
                                res = &dev->resource[1];
                                res->flags = LEGACY_IO_RESOURCE;
                                pcibios_bus_to_resource(dev->bus, res, ®ion);
-                               pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
+                               pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n",
                                         res);
                        }
                        if ((progif & 4) == 0) {
                                res = &dev->resource[2];
                                res->flags = LEGACY_IO_RESOURCE;
                                pcibios_bus_to_resource(dev->bus, res, ®ion);
-                               pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
+                               pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n",
                                         res);
                                region.start = 0x376;
                                region.end = 0x376;
                                res = &dev->resource[3];
                                res->flags = LEGACY_IO_RESOURCE;
                                pcibios_bus_to_resource(dev->bus, res, ®ion);
-                               pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
+                               pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n",
                                         res);
                        }
                }
 
 
        for (i = 0; i < PCI_STD_NUM_BARS; i++) {
                struct resource *r = &dev->resource[i];
+               const char *r_name = pci_resource_name(dev, i);
 
                if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
                        r->end = PAGE_SIZE - 1;
                        r->start = 0;
                        r->flags |= IORESOURCE_UNSET;
-                       pci_info(dev, "expanded BAR %d to page size: %pR\n",
-                                i, r);
+                       pci_info(dev, "%s %pR: expanded to page size\n",
+                                r_name, r);
                }
        }
 }
        u32 region;
        struct pci_bus_region bus_region;
        struct resource *res = dev->resource + pos;
+       const char *res_name = pci_resource_name(dev, pos);
 
        pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
 
        bus_region.end = region + size - 1;
        pcibios_bus_to_resource(dev->bus, res, &bus_region);
 
-       pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
-                name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
+       pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name);
 }
 
 /*
        bus_region.end = region + size - 1;
        pcibios_bus_to_resource(dev->bus, res, &bus_region);
 
+       /*
+        * "res" is typically a bridge window resource that's not being
+        * used for a bridge window, so it's just a place to stash this
+        * non-standard resource.  Printing "nr" or pci_resource_name() of
+        * it doesn't really make sense.
+        */
        if (!pci_claim_resource(dev, nr))
                pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
 }
 
                                      struct list_head *head)
 {
        struct resource *res;
+       const char *res_name;
        struct pci_dev_resource *add_res, *tmp;
        struct pci_dev_resource *dev_res;
        resource_size_t add_size, align;
                bool found_match = false;
 
                res = add_res->res;
+
                /* Skip resource that has been reset */
                if (!res->flags)
                        goto out;
                        continue;
 
                idx = res - &add_res->dev->resource[0];
+               res_name = pci_resource_name(add_res->dev, idx);
                add_size = add_res->add_size;
                align = add_res->min_align;
                if (!resource_size(res)) {
                                 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
                        if (pci_reassign_resource(add_res->dev, idx,
                                                  add_size, align))
-                               pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
-                                        (unsigned long long) add_size, idx,
-                                        res);
+                               pci_info(add_res->dev, "%s %pR: failed to add %llx\n",
+                                        res_name, res,
+                                        (unsigned long long) add_size);
                }
 out:
                list_del(&add_res->list);
 static void pci_setup_bridge_io(struct pci_dev *bridge)
 {
        struct resource *res;
+       const char *res_name;
        struct pci_bus_region region;
        unsigned long io_mask;
        u8 io_base_lo, io_limit_lo;
 
        /* Set up the top and bottom of the PCI I/O segment for this bus */
        res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
+       res_name = pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW);
        pcibios_resource_to_bus(bridge->bus, ®ion, res);
        if (res->flags & IORESOURCE_IO) {
                pci_read_config_word(bridge, PCI_IO_BASE, &l);
                l = ((u16) io_limit_lo << 8) | io_base_lo;
                /* Set up upper 16 bits of I/O base/limit */
                io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
-               pci_info(bridge, "  bridge window %pR\n", res);
+               pci_info(bridge, "  %s %pR\n", res_name, res);
        } else {
                /* Clear upper 16 bits of I/O base/limit */
                io_upper16 = 0;
 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
 {
        struct resource *res;
+       const char *res_name;
        struct pci_bus_region region;
        u32 l;
 
        /* Set up the top and bottom of the PCI Memory segment for this bus */
        res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
+       res_name = pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW);
        pcibios_resource_to_bus(bridge->bus, ®ion, res);
        if (res->flags & IORESOURCE_MEM) {
                l = (region.start >> 16) & 0xfff0;
                l |= region.end & 0xfff00000;
-               pci_info(bridge, "  bridge window %pR\n", res);
+               pci_info(bridge, "  %s %pR\n", res_name, res);
        } else {
                l = 0x0000fff0;
        }
 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
 {
        struct resource *res;
+       const char *res_name;
        struct pci_bus_region region;
        u32 l, bu, lu;
 
        /* Set up PREF base/limit */
        bu = lu = 0;
        res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
+       res_name = pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW);
        pcibios_resource_to_bus(bridge->bus, ®ion, res);
        if (res->flags & IORESOURCE_PREFETCH) {
                l = (region.start >> 16) & 0xfff0;
                        bu = upper_32_bits(region.start);
                        lu = upper_32_bits(region.end);
                }
-               pci_info(bridge, "  bridge window %pR\n", res);
+               pci_info(bridge, "  %s %pR\n", res_name, res);
        } else {
                l = 0x0000fff0;
        }
                int i;
 
                pci_dev_for_each_resource(dev, r, i) {
+                       const char *r_name = pci_resource_name(dev, i);
                        resource_size_t r_size;
 
                        if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
                        if (order < 0)
                                order = 0;
                        if (order >= ARRAY_SIZE(aligns)) {
-                               pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
-                                        i, r, (unsigned long long) align);
+                               pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n",
+                                        r_name, r, (unsigned long long) align);
                                r->flags = 0;
                                continue;
                        }
                for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
                     i++) {
                        struct resource *res = &bridge->resource[i];
+                       const char *res_name = pci_resource_name(bridge, i);
 
                        if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
                                continue;
                        if (ret)
                                goto cleanup;
 
-                       pci_info(bridge, "BAR %d: releasing %pR\n",
-                                i, res);
+                       pci_info(bridge, "%s %pR: releasing\n", res_name, res);
 
                        if (res->parent)
                                release_resource(res);
 
        u32 new, check, mask;
        int reg;
        struct resource *res = dev->resource + resno;
+       const char *res_name = pci_resource_name(dev, resno);
 
        /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
        if (dev->is_virtfn)
        pci_read_config_dword(dev, reg, &check);
 
        if ((new ^ check) & mask) {
-               pci_err(dev, "BAR %d: error updating (%#010x != %#010x)\n",
-                       resno, new, check);
+               pci_err(dev, "%s: error updating (%#010x != %#010x)\n",
+                       res_name, new, check);
        }
 
        if (res->flags & IORESOURCE_MEM_64) {
                pci_write_config_dword(dev, reg + 4, new);
                pci_read_config_dword(dev, reg + 4, &check);
                if (check != new) {
-                       pci_err(dev, "BAR %d: error updating (high %#010x != %#010x)\n",
-                               resno, new, check);
+                       pci_err(dev, "%s: error updating (high %#010x != %#010x)\n",
+                               res_name, new, check);
                }
        }
 
 int pci_claim_resource(struct pci_dev *dev, int resource)
 {
        struct resource *res = &dev->resource[resource];
+       const char *res_name = pci_resource_name(dev, resource);
        struct resource *root, *conflict;
 
        if (res->flags & IORESOURCE_UNSET) {
-               pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
-                        resource, res);
+               pci_info(dev, "%s %pR: can't claim; no address assigned\n",
+                        res_name, res);
                return -EINVAL;
        }
 
 
        root = pci_find_parent_resource(dev, res);
        if (!root) {
-               pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
-                        resource, res);
+               pci_info(dev, "%s %pR: can't claim; no compatible bridge window\n",
+                        res_name, res);
                res->flags |= IORESOURCE_UNSET;
                return -EINVAL;
        }
 
        conflict = request_resource_conflict(root, res);
        if (conflict) {
-               pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
-                        resource, res, conflict->name, conflict);
+               pci_info(dev, "%s %pR: can't claim; address conflict with %s %pR\n",
+                        res_name, res, conflict->name, conflict);
                res->flags |= IORESOURCE_UNSET;
                return -EBUSY;
        }
 {
        struct resource *root, *conflict;
        resource_size_t fw_addr, start, end;
+       const char *res_name = pci_resource_name(dev, resno);
 
        fw_addr = pcibios_retrieve_fw_addr(dev, resno);
        if (!fw_addr)
                        root = &iomem_resource;
        }
 
-       pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
-                resno, res);
+       pci_info(dev, "%s: trying firmware assignment %pR\n", res_name, res);
        conflict = request_resource_conflict(root, res);
        if (conflict) {
-               pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
-                        resno, res, conflict->name, conflict);
+               pci_info(dev, "%s %pR: conflicts with %s %pR\n", res_name, res,
+                        conflict->name, conflict);
                res->start = start;
                res->end = end;
                res->flags |= IORESOURCE_UNSET;
 int pci_assign_resource(struct pci_dev *dev, int resno)
 {
        struct resource *res = dev->resource + resno;
+       const char *res_name = pci_resource_name(dev, resno);
        resource_size_t align, size;
        int ret;
 
        res->flags |= IORESOURCE_UNSET;
        align = pci_resource_alignment(dev, res);
        if (!align) {
-               pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
-                        resno, res);
+               pci_info(dev, "%s %pR: can't assign; bogus alignment\n",
+                        res_name, res);
                return -EINVAL;
        }
 
         * working, which is better than just leaving it disabled.
         */
        if (ret < 0) {
-               pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
+               pci_info(dev, "%s %pR: can't assign; no space\n", res_name, res);
                ret = pci_revert_fw_address(res, dev, resno, size);
        }
 
        if (ret < 0) {
-               pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
+               pci_info(dev, "%s %pR: failed to assign\n", res_name, res);
                return ret;
        }
 
        res->flags &= ~IORESOURCE_UNSET;
        res->flags &= ~IORESOURCE_STARTALIGN;
-       pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
+       pci_info(dev, "%s %pR: assigned\n", res_name, res);
        if (resno < PCI_BRIDGE_RESOURCES)
                pci_update_resource(dev, resno);
 
 }
 EXPORT_SYMBOL(pci_assign_resource);
 
-int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
-                       resource_size_t min_align)
+int pci_reassign_resource(struct pci_dev *dev, int resno,
+                         resource_size_t addsize, resource_size_t min_align)
 {
        struct resource *res = dev->resource + resno;
+       const char *res_name = pci_resource_name(dev, resno);
        unsigned long flags;
        resource_size_t new_size;
        int ret;
        flags = res->flags;
        res->flags |= IORESOURCE_UNSET;
        if (!res->parent) {
-               pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
-                        resno, res);
+               pci_info(dev, "%s %pR: can't reassign; unassigned resource\n",
+                        res_name, res);
                return -EINVAL;
        }
 
        ret = _pci_assign_resource(dev, resno, new_size, min_align);
        if (ret) {
                res->flags = flags;
-               pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
-                        resno, res, (unsigned long long) addsize);
+               pci_info(dev, "%s %pR: failed to expand by %#llx\n",
+                        res_name, res, (unsigned long long) addsize);
                return ret;
        }
 
        res->flags &= ~IORESOURCE_UNSET;
        res->flags &= ~IORESOURCE_STARTALIGN;
-       pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
-                resno, res, (unsigned long long) addsize);
+       pci_info(dev, "%s %pR: reassigned; expanded by %#llx\n",
+                res_name, res, (unsigned long long) addsize);
        if (resno < PCI_BRIDGE_RESOURCES)
                pci_update_resource(dev, resno);
 
 void pci_release_resource(struct pci_dev *dev, int resno)
 {
        struct resource *res = dev->resource + resno;
+       const char *res_name = pci_resource_name(dev, resno);
 
-       pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
+       pci_info(dev, "%s %pR: releasing\n", res_name, res);
 
        if (!res->parent)
                return;
        u16 cmd, old_cmd;
        int i;
        struct resource *r;
+       const char *r_name;
 
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
        old_cmd = cmd;
                if (!(mask & (1 << i)))
                        continue;
 
+               r_name = pci_resource_name(dev, i);
+
                if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
                        continue;
                if ((i == PCI_ROM_RESOURCE) &&
                        continue;
 
                if (r->flags & IORESOURCE_UNSET) {
-                       pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
-                               i, r);
+                       pci_err(dev, "%s %pR: not assigned; can't enable device\n",
+                               r_name, r);
                        return -EINVAL;
                }
 
                if (!r->parent) {
-                       pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
-                               i, r);
+                       pci_err(dev, "%s %pR: not claimed; can't enable device\n",
+                               r_name, r);
                        return -EINVAL;
                }