KVM VMX: Move MSR_IA32_VMX_MISC bit defines to asm/vmx.h

Move the handful of MSR_IA32_VMX_MISC bit defines that are currently in
msr-indx.h to vmx.h so that all of the VMX_MISC defines and wrappers can
be found in a single location.

Opportunistically use BIT_ULL() instead of open coding hex values, add
defines for feature bits that are architecturally defined, and move the
defines down in the file so that they are colocated with the helpers for
getting fields from VMX_MISC.

No functional change intended.

Cc: Shan Kang <shan.kang@intel.com>
Cc: Kai Huang <kai.huang@intel.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
[sean: split to separate patch, write changelog]
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Kai Huang <kai.huang@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Link: https://lore.kernel.org/r/20240605231918.2915961-9-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ad0b579d1c01d8109ccc640d072894f14b71de6f..72c2c0ecb62c8af405ac14d86ddf5874350f8b79 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -1194,11 +1194,6 @@
 #define MSR_IA32_SMBA_BW_BASE          0xc0000280
 #define MSR_IA32_EVT_CFG_BASE          0xc0000400
 
-/* MSR_IA32_VMX_MISC bits */
-#define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)
-#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
-#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F
-
 /* AMD-V MSRs */
 #define MSR_VM_CR                       0xc0010114
 #define MSR_VM_IGNNE                    0xc0010115

diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 65aaf0577265421f71bfae12c4479e45ac45686c..400819ccb42c30f43f96d4a7622ac537d90d2045 100644 (file)
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -122,13 +122,6 @@
 
 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR     0x000011ff
 
-#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK    0x0000001f
-#define VMX_MISC_SAVE_EFER_LMA                 0x00000020
-#define VMX_MISC_ACTIVITY_HLT                  0x00000040
-#define VMX_MISC_ACTIVITY_WAIT_SIPI            0x00000100
-#define VMX_MISC_ZERO_LEN_INS                  0x40000000
-#define VMX_MISC_MSR_LIST_MULTIPLIER           512
-
 /* VMFUNC functions */
 #define VMFUNC_CONTROL_BIT(x)  BIT((VMX_FEATURE_##x & 0x1f) - 28)
 
@@ -160,6 +153,18 @@ static inline u64 vmx_basic_encode_vmcs_info(u32 revision, u16 size, u8 memtype)
        return revision | ((u64)size << 32) | ((u64)memtype << 50);
 }
 
+#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK    GENMASK_ULL(4, 0)
+#define VMX_MISC_SAVE_EFER_LMA                 BIT_ULL(5)
+#define VMX_MISC_ACTIVITY_HLT                  BIT_ULL(6)
+#define VMX_MISC_ACTIVITY_SHUTDOWN             BIT_ULL(7)
+#define VMX_MISC_ACTIVITY_WAIT_SIPI            BIT_ULL(8)
+#define VMX_MISC_INTEL_PT                      BIT_ULL(14)
+#define VMX_MISC_RDMSR_IN_SMM                  BIT_ULL(15)
+#define VMX_MISC_VMXOFF_BLOCK_SMI              BIT_ULL(28)
+#define VMX_MISC_VMWRITE_SHADOW_RO_FIELDS      BIT_ULL(29)
+#define VMX_MISC_ZERO_LEN_INS                  BIT_ULL(30)
+#define VMX_MISC_MSR_LIST_MULTIPLIER           512
+
 static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
 {
        return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;

diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
index 86ce8bb96bed7bd5209893aa89b4c581c1f6a678..cb6588238f4667fa13902d2efc3fe29749fce71d 100644 (file)
--- a/arch/x86/kvm/vmx/capabilities.h
+++ b/arch/x86/kvm/vmx/capabilities.h
@@ -223,7 +223,7 @@ static inline bool cpu_has_vmx_vmfunc(void)
 static inline bool cpu_has_vmx_shadow_vmcs(void)
 {
        /* check if the cpu supports writing r/o exit information fields */
-       if (!(vmcs_config.misc & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
+       if (!(vmcs_config.misc & VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
                return false;
 
        return vmcs_config.cpu_based_2nd_exec_ctrl &
@@ -365,7 +365,7 @@ static inline bool cpu_has_vmx_invvpid_global(void)
 
 static inline bool cpu_has_vmx_intel_pt(void)
 {
-       return (vmcs_config.misc & MSR_IA32_VMX_MISC_INTEL_PT) &&
+       return (vmcs_config.misc & VMX_MISC_INTEL_PT) &&
                (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) &&
                (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL);
 }

diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 335f1a650497735c8ef36e8afdf42cd57da252a1..72db3718d8b210b57160600124e09245c32c897d 100644 (file)
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -7062,7 +7062,7 @@ static void nested_vmx_setup_misc_data(struct vmcs_config *vmcs_conf,
 {
        msrs->misc_low = (u32)vmcs_conf->misc & VMX_MISC_SAVE_EFER_LMA;
        msrs->misc_low |=
-               MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
+               VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
                VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
                VMX_MISC_ACTIVITY_HLT |
                VMX_MISC_ACTIVITY_WAIT_SIPI;

diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h
index cce4e2aa30fbf8b98b114a069ef8445cb2b9aaf4..0782fe599757aeb73c0f749e01e431038b3a162f 100644 (file)
--- a/arch/x86/kvm/vmx/nested.h
+++ b/arch/x86/kvm/vmx/nested.h
@@ -109,7 +109,7 @@ static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
 {
        return to_vmx(vcpu)->nested.msrs.misc_low &
-               MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
+               VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
 }
 
 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)