};
 
 struct armada37xx_cpufreq_state {
+       struct platform_device *pdev;
+       struct device *cpu_dev;
        struct regmap *regmap;
        u32 nb_l0l1;
        u32 nb_l2l3;
        if (ret)
                goto disable_dvfs;
 
+       armada37xx_cpufreq_state->cpu_dev = cpu_dev;
+       armada37xx_cpufreq_state->pdev = pdev;
+       platform_set_drvdata(pdev, dvfs);
        return 0;
 
 disable_dvfs:
 /* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
 late_initcall(armada37xx_cpufreq_driver_init);
 
+static void __exit armada37xx_cpufreq_driver_exit(void)
+{
+       struct platform_device *pdev = armada37xx_cpufreq_state->pdev;
+       struct armada_37xx_dvfs *dvfs = platform_get_drvdata(pdev);
+       unsigned long freq;
+       int load_lvl;
+
+       platform_device_unregister(pdev);
+
+       armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap);
+
+       for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
+               freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl];
+               dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq);
+       }
+
+       kfree(armada37xx_cpufreq_state);
+}
+module_exit(armada37xx_cpufreq_driver_exit);
+
 static const struct of_device_id __maybe_unused armada37xx_cpufreq_of_match[] = {
        { .compatible = "marvell,armada-3700-nb-pm" },
        { },