#define hnae3_dev_stash_supported(hdev) \
        test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
 
+#define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \
+       test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)
+
 #define ring_ptr_move_fw(ring, p) \
        ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
 #define ring_ptr_move_bw(ring, p) \
 
 static int hns3_dbg_queue_info(struct hnae3_handle *h,
                               const char *cmd_buf)
 {
+       struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
        struct hns3_nic_priv *priv = h->priv;
        struct hns3_enet_ring *ring;
        u32 base_add_l, base_add_h;
 
                value = readl_relaxed(ring->tqp->io_base +
                                      HNS3_RING_TX_RING_PKTNUM_RECORD_REG);
-               dev_info(&h->pdev->dev, "TX(%u) RING PKTNUM: %u\n\n", i,
-                        value);
+               dev_info(&h->pdev->dev, "TX(%u) RING PKTNUM: %u\n", i, value);
+
+               value = readl_relaxed(ring->tqp->io_base + HNS3_RING_EN_REG);
+               dev_info(&h->pdev->dev, "TX/RX(%u) RING EN: %s\n", i,
+                        value ? "enable" : "disable");
+
+               if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) {
+                       value = readl_relaxed(ring->tqp->io_base +
+                                             HNS3_RING_TX_EN_REG);
+                       dev_info(&h->pdev->dev, "TX(%u) RING EN: %s\n", i,
+                                value ? "enable" : "disable");
+
+                       value = readl_relaxed(ring->tqp->io_base +
+                                             HNS3_RING_RX_EN_REG);
+                       dev_info(&h->pdev->dev, "RX(%u) RING EN: %s\n", i,
+                                value ? "enable" : "disable");
+               }
+
+               dev_info(&h->pdev->dev, "\n");
        }
 
        return 0;
 
 #define HNS3_RING_TX_RING_EBD_OFFSET_REG       0x00070
 #define HNS3_RING_TX_RING_BD_ERR_REG           0x00074
 #define HNS3_RING_EN_REG                       0x00090
+#define HNS3_RING_RX_EN_REG                    0x00098
+#define HNS3_RING_TX_EN_REG                    0x000D4
 
 #define HNS3_RX_HEAD_SIZE                      256