drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_SRCSZ_ERLY_TPT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b37217f55702fc10190c2c5aded7d845a36766f6.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 23a122ee20c98d60aa6410fdcedf41923834fb51..2118b87ccb1004b18ab9ad5a0570761a1a169f15 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
 
        intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
 
-       intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
+       intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
                       PIPESRC_HEIGHT(et_y_position));
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 638f01f0c328e3612b44994a2eb2d5d3ff4193f6..e3221cd5bf579252d6934ea560d1c81dfb2b5ac4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2303,7 +2303,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
        if (!crtc_state->enable_psr2_su_region_et)
                return;
 
-       intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
+       intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe),
                       crtc_state->pipe_srcsz_early_tpt);
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index db990f30f0d550430e213158ef7694040e6e67b6..a10cf5120efbf2d0f582db574e127891ff1da984 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -249,7 +249,7 @@
 /* PSR2 Early transport */
 #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
 
-#define PIPE_SRCSZ_ERLY_TPT(trans)     _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
+#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans)   _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
 
 #define _SEL_FETCH_PLANE_BASE_1_A              0x70890
 #define _SEL_FETCH_PLANE_BASE_2_A              0x708B0