drm/i915: Check if the stolen memory "reserved" area is enabled or not

Apparently there are some machines that put semi-sensible looking values
into the stolen "reserved" base and size, except those values are actually
outside the stolen memory. There is a bit in the register which
supposedly could tell us whether the reserved area is even enabled or
not. Let's check for that before we go trusting the base and size.

Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171102151737.23336-1-ville.syrjala@linux.intel.com
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 03e7abc7e043a5f24d8ce9f7f4b0f8e00247c7c2..44a5dbc8c23b11ca7350ee4565c3e868d406d634 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -294,6 +294,12 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
                                     ELK_STOLEN_RESERVED);
        dma_addr_t stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
 
+       if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) {
+               *base = 0;
+               *size = 0;
+               return;
+       }
+
        *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
 
        WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
@@ -313,6 +319,12 @@ static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv,
 {
        uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
 
+       if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
+               *base = 0;
+               *size = 0;
+               return;
+       }
+
        *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
 
        switch (reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK) {
@@ -339,6 +351,12 @@ static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv,
 {
        uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
 
+       if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
+               *base = 0;
+               *size = 0;
+               return;
+       }
+
        *base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK;
 
        switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
@@ -359,6 +377,12 @@ static void chv_get_stolen_reserved(struct drm_i915_private *dev_priv,
 {
        uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
 
+       if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
+               *base = 0;
+               *size = 0;
+               return;
+       }
+
        *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
 
        switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
@@ -387,6 +411,12 @@ static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv,
        uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
        dma_addr_t stolen_top;
 
+       if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
+               *base = 0;
+               *size = 0;
+               return;
+       }
+
        stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
 
        *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cfdf4f821ac3ac7b7ea94241941f586a414846ee..107e2d7c9fba72f4600029698a8ccf7743317dfb 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -379,6 +379,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN8_STOLEN_RESERVED_2M                (1 << 7)
 #define GEN8_STOLEN_RESERVED_4M                (2 << 7)
 #define GEN8_STOLEN_RESERVED_8M                (3 << 7)
+#define GEN6_STOLEN_RESERVED_ENABLE    (1 << 0)
 
 /* VGA stuff */
 
@@ -3431,6 +3432,7 @@ enum i915_power_well_id {
 #define ELK_STOLEN_RESERVED            _MMIO(MCHBAR_MIRROR_BASE + 0x48)
 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
+#define G4X_STOLEN_RESERVED_ENABLE     (1 << 0)
 
 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)