clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value

Product datasheet recommends different values for UPLL and PLLA analog control
register.
Adapt accordingly.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1573478913-19737-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index 34b817825b22f62af23a1204f64b7b27171c1af3..dfb354a5ff1866e8da2eb5161df13c0919fab786 100644 (file)
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -25,7 +25,8 @@
 #define                PMC_PLL_CTRL1_MUL_MSK           GENMASK(30, 24)
 
 #define PMC_PLL_ACR    0x18
-#define                PMC_PLL_ACR_DEFAULT             0x1b040010UL
+#define                PMC_PLL_ACR_DEFAULT_UPLL        0x12020010UL
+#define                PMC_PLL_ACR_DEFAULT_PLLA        0x00020010UL
 #define                PMC_PLL_ACR_UTMIVR              BIT(12)
 #define                PMC_PLL_ACR_UTMIBG              BIT(13)
 #define                PMC_PLL_ACR_LOOP_FILTER_MSK     GENMASK(31, 24)
@@ -88,7 +89,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
        }
 
        /* Recommended value for PMC_PLL_ACR */
-       val = PMC_PLL_ACR_DEFAULT;
+       if (pll->characteristics->upll)
+               val = PMC_PLL_ACR_DEFAULT_UPLL;
+       else
+               val = PMC_PLL_ACR_DEFAULT_PLLA;
        regmap_write(regmap, PMC_PLL_ACR, val);
 
        regmap_write(regmap, PMC_PLL_CTRL1,