.mfilt1 = CCDC_NO_MEDIAN_FILTER1,
                        .mfilt2 = CCDC_NO_MEDIAN_FILTER2,
                        .alaw = {
-                               .gama_wd = 2,
+                               .gamma_wd = 2,
                        },
                        .blk_clamp = {
                                .sample_pixel = 1,
        }
 
        if (ccdcparam->alaw.enable) {
-               if (ccdcparam->alaw.gama_wd < CCDC_GAMMA_BITS_13_4 ||
-                   ccdcparam->alaw.gama_wd > CCDC_GAMMA_BITS_09_0) {
+               if (ccdcparam->alaw.gamma_wd < CCDC_GAMMA_BITS_13_4 ||
+                   ccdcparam->alaw.gamma_wd > CCDC_GAMMA_BITS_09_0) {
                        dev_dbg(ccdc_cfg.dev, "Invalid value of ALAW\n");
                        return -EINVAL;
                }
        /* Enable and configure aLaw register if needed */
        if (config_params->alaw.enable) {
                val |= (CCDC_ALAW_ENABLE |
-                       ((config_params->alaw.gama_wd &
-                       CCDC_ALAW_GAMA_WD_MASK) <<
+                       ((config_params->alaw.gamma_wd &
+                       CCDC_ALAW_GAMMA_WD_MASK) <<
                        CCDC_GAMMAWD_INPUT_SHIFT));
        }
 
 
 #define CCDC_VDHDEN_ENABLE                     (1 << 16)
 #define CCDC_LPF_ENABLE                                (1 << 14)
 #define CCDC_ALAW_ENABLE                       1
-#define CCDC_ALAW_GAMA_WD_MASK                 7
+#define CCDC_ALAW_GAMMA_WD_MASK                        7
 #define CCDC_REC656IF_BT656_EN                 3
 
 #define CCDC_FMTCFG_FMTMODE_MASK               3
 
        if (module_params->compress.alg == ISIF_ALAW)
                val |= ISIF_ALAW_ENABLE;
 
-       val |= (params->data_msb << ISIF_ALAW_GAMA_WD_SHIFT);
+       val |= (params->data_msb << ISIF_ALAW_GAMMA_WD_SHIFT);
        regw(val, CGAMMAWD);
 
        /* Configure DPCM compression settings */
 
 #define ISIF_LPF_MASK                          1
 
 /* GAMMAWD registers */
-#define ISIF_ALAW_GAMA_WD_MASK                 0xF
-#define ISIF_ALAW_GAMA_WD_SHIFT                        1
+#define ISIF_ALAW_GAMMA_WD_MASK                        0xF
+#define ISIF_ALAW_GAMMA_WD_SHIFT               1
 #define ISIF_ALAW_ENABLE                       1
 #define ISIF_GAMMAWD_CFA_SHIFT                 5
 
 
        CCDC_SAMPLE_16LINES
 };
 
-/* enum for Alaw gama width */
+/* enum for Alaw gamma width */
 enum ccdc_gamma_width {
        CCDC_GAMMA_BITS_13_4,
        CCDC_GAMMA_BITS_12_3,
 struct ccdc_a_law {
        /* Enable/disable A-Law */
        unsigned char enable;
-       /* Gama Width Input */
-       enum ccdc_gamma_width gama_wd;
+       /* Gamma Width Input */
+       enum ccdc_gamma_width gamma_wd;
 };
 
 /* structure for Black Clamping */