u8 kvd_hash_single_parts;
u8 kvd_hash_double_parts;
u8 cqe_time_stamp_type;
+ bool lag_mode_prefer_sw;
struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT];
};
profile->cqe_time_stamp_type);
}
- mlxsw_pci->lag_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_FW;
+ if (profile->lag_mode_prefer_sw && mlxsw_pci->lag_mode_support) {
+ enum mlxsw_cmd_mbox_config_profile_lag_mode lag_mode =
+ MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW;
+
+ mlxsw_cmd_mbox_config_profile_set_lag_mode_set(mbox, 1);
+ mlxsw_cmd_mbox_config_profile_lag_mode_set(mbox, lag_mode);
+ mlxsw_pci->lag_mode = lag_mode;
+ } else {
+ mlxsw_pci->lag_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_FW;
+ }
return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
}
if (err)
goto err_config_profile;
- /* Some resources depend on unified bridge model, which is configured
- * as part of config_profile. Query the resources again to get correct
- * values.
+ /* Some resources depend on details of config_profile, such as unified
+ * bridge model. Query the resources again to get correct values.
*/
err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
if (err)