ASoC: jz4740-i2s: Align macro values and sort includes

Some purely cosmetic changes: line up all the macro values to
make things easier to read and sort the includes alphabetically.

Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221023143328.160866-6-aidanmacdonald.0x0@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c
index 4767abea425fd31fac42da03325e64e430ce62b9..c3235e993ffb703a97499d034a0ae4aac624d555 100644 (file)
--- a/sound/soc/jz4740/jz4740-i2s.c
+++ b/sound/soc/jz4740/jz4740-i2s.c
@@ -4,6 +4,9 @@
  */
 
 #include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
@@ -13,11 +16,6 @@
 #include <linux/regmap.h>
 #include <linux/slab.h>
 
-#include <linux/clk.h>
-#include <linux/delay.h>
-
-#include <linux/dma-mapping.h>
-
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -35,37 +33,37 @@
 #define JZ_REG_AIC_CLK_DIV     0x30
 #define JZ_REG_AIC_FIFO                0x34
 
-#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
-#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
-#define JZ_AIC_CONF_I2S BIT(4)
-#define JZ_AIC_CONF_RESET BIT(3)
-#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
-#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
-#define JZ_AIC_CONF_ENABLE BIT(0)
-
-#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19)
-#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16)
-#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
-#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
-#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
-#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
-#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
+#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
+#define JZ_AIC_CONF_INTERNAL_CODEC     BIT(5)
+#define JZ_AIC_CONF_I2S                        BIT(4)
+#define JZ_AIC_CONF_RESET              BIT(3)
+#define JZ_AIC_CONF_BIT_CLK_MASTER     BIT(2)
+#define JZ_AIC_CONF_SYNC_CLK_MASTER    BIT(1)
+#define JZ_AIC_CONF_ENABLE             BIT(0)
+
+#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19)
+#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE  GENMASK(18, 16)
+#define JZ_AIC_CTRL_ENABLE_RX_DMA      BIT(15)
+#define JZ_AIC_CTRL_ENABLE_TX_DMA      BIT(14)
+#define JZ_AIC_CTRL_MONO_TO_STEREO     BIT(11)
+#define JZ_AIC_CTRL_SWITCH_ENDIANNESS  BIT(10)
+#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
 #define JZ_AIC_CTRL_TFLUSH             BIT(8)
 #define JZ_AIC_CTRL_RFLUSH             BIT(7)
-#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
-#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
-#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
-#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
-#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
-#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
-#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
-
-#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
-#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
-#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
-#define JZ_AIC_I2S_FMT_MSB BIT(0)
-
-#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
+#define JZ_AIC_CTRL_ENABLE_ROR_INT     BIT(6)
+#define JZ_AIC_CTRL_ENABLE_TUR_INT     BIT(5)
+#define JZ_AIC_CTRL_ENABLE_RFS_INT     BIT(4)
+#define JZ_AIC_CTRL_ENABLE_TFS_INT     BIT(3)
+#define JZ_AIC_CTRL_ENABLE_LOOPBACK    BIT(2)
+#define JZ_AIC_CTRL_ENABLE_PLAYBACK    BIT(1)
+#define JZ_AIC_CTRL_ENABLE_CAPTURE     BIT(0)
+
+#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
+#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK        BIT(13)
+#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK  BIT(4)
+#define JZ_AIC_I2S_FMT_MSB             BIT(0)
+
+#define JZ_AIC_I2S_STATUS_BUSY         BIT(2)
 
 struct i2s_soc_info {
        struct snd_soc_dai_driver *dai;