scsi: ufs: host: ufs-exynos: Add mphy apb clock mask

Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
during clock masking/unmasking.

Link: https://lore.kernel.org/r/20220610104119.66401-6-alim.akhtar@samsung.com
Tested-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index a81d8cbd542f38e7a82bbe58437621aa6029374b..cc128aff8871d92e9f860d40d75d61dfe34568b7 100644 (file)
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -52,11 +52,12 @@
 #define HCI_ERR_EN_DME_LAYER   0x88
 #define HCI_CLKSTOP_CTRL       0xB0
 #define REFCLKOUT_STOP         BIT(4)
+#define MPHY_APBCLK_STOP       BIT(3)
 #define REFCLK_STOP            BIT(2)
 #define UNIPRO_MCLK_STOP       BIT(1)
 #define UNIPRO_PCLK_STOP       BIT(0)
 #define CLK_STOP_MASK          (REFCLKOUT_STOP | REFCLK_STOP |\
-                                UNIPRO_MCLK_STOP |\
+                                UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
                                 UNIPRO_PCLK_STOP)
 #define HCI_MISC               0xB4
 #define REFCLK_CTRL_EN         BIT(7)