In NICs that don't support LAG, the LAG control structure won't be
allocated. If it wasn't allocated it means LAG doesn't exists and can be
skipped.
Fixes: cac1eb2cf2e3 ("net/mlx5: Lag, properly lock eswitch if needed")
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Maor Gottlieb <maorg@nvidia.com>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
        struct mlx5_core_dev *dev1;
        struct mlx5_lag *ldev;
 
+       ldev = mlx5_lag_dev(dev);
+       if (!ldev)
+               return;
+
        mlx5_dev_list_lock();
 
-       ldev = mlx5_lag_dev(dev);
        dev0 = ldev->pf[MLX5_LAG_P1].dev;
        dev1 = ldev->pf[MLX5_LAG_P2].dev;
 
 {
        struct mlx5_lag *ldev;
 
-       mlx5_dev_list_lock();
        ldev = mlx5_lag_dev(dev);
+       if (!ldev)
+               return;
+
+       mlx5_dev_list_lock();
        ldev->mode_changes_in_progress--;
        mlx5_dev_list_unlock();
        mlx5_queue_bond_work(ldev, 0);