net: renesas: rswitch: use FIELD_PREP for remaining MPIC register fields

Commit fb9e6039c325 ("net: renesas: rswitch: fix initial MPIC register
setting") converted setting some MPIC fields to FIELD_PREP.

To keep common style, do the same with mii bus related fields of the
same register.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://patch.msgid.link/20241216071957.2587354-3-nikita.yoush@cogentembedded.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/renesas/rswitch.c
index 12efee9f75d82e86b10ef21754c4448625b9bb84..e1541a206687cd3a62ddefc5b0e971fdc6e6eef5 100644 (file)
--- a/drivers/net/ethernet/renesas/rswitch.c
+++ b/drivers/net/ethernet/renesas/rswitch.c
@@ -1164,8 +1164,9 @@ static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
 
 static void rswitch_etha_enable_mii(struct rswitch_etha *etha)
 {
-       rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
-                      MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06));
+       rswitch_modify(etha->addr, MPIC, MPIC_PSMCS | MPIC_PSMHT,
+                      FIELD_PREP(MPIC_PSMCS, etha->psmcs) |
+                      FIELD_PREP(MPIC_PSMHT, 0x06));
 }
 
 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac)

diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/renesas/rswitch.h
index 4b14891003304de810caf35062b8aefeac88b965..78c0325cdf3062fa88ee93d6d22114bc237a798d 100644 (file)
--- a/drivers/net/ethernet/renesas/rswitch.h
+++ b/drivers/net/ethernet/renesas/rswitch.h
@@ -732,6 +732,8 @@ enum rswitch_etha_mode {
 #define MPIC_LSC_100M          1
 #define MPIC_LSC_1G            2
 #define MPIC_LSC_2_5G          3
+#define MPIC_PSMCS             GENMASK(22, 16)
+#define MPIC_PSMHT             GENMASK(26, 24)
 
 #define MDIO_READ_C45          0x03
 #define MDIO_WRITE_C45         0x01
@@ -747,14 +749,6 @@ enum rswitch_etha_mode {
 #define MMIS1_PRACS             BIT(0) /* Read */
 #define MMIS1_CLEAR_FLAGS       0xf
 
-#define MPIC_PSMCS_SHIFT       16
-#define MPIC_PSMCS_MASK                GENMASK(22, MPIC_PSMCS_SHIFT)
-#define MPIC_PSMCS(val)                ((val) << MPIC_PSMCS_SHIFT)
-
-#define MPIC_PSMHT_SHIFT       24
-#define MPIC_PSMHT_MASK                GENMASK(26, MPIC_PSMHT_SHIFT)
-#define MPIC_PSMHT(val)                ((val) << MPIC_PSMHT_SHIFT)
-
 #define MLVC_PLV               BIT(16)
 
 /* GWCA */