clk_set_rate(plat->stmmac_clk, 50000000);
        }
 
-       if (plat->phy_node && bsp_priv->integrated_phy) {
+       if (plat->phy_node) {
                bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
                ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
-               if (ret)
-                       return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
-               clk_set_rate(bsp_priv->clk_phy, 50000000);
+               /* If it is not integrated_phy, clk_phy is optional */
+               if (bsp_priv->integrated_phy) {
+                       if (ret)
+                               return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
+                       clk_set_rate(bsp_priv->clk_phy, 50000000);
+               }
        }
 
        return 0;