{
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct kv_power_info *pi = kv_get_pi(adev);
-       int ret;
 
        pi->uvd_power_gated = gate;
 
        if (gate) {
                /* stop the UVD block */
-               ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                            AMD_PG_STATE_GATE);
+               amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                      AMD_PG_STATE_GATE);
                kv_update_uvd_dpm(adev, gate);
                if (pi->caps_uvd_pg)
                        /* power off the UVD block */
                        /* re-init the UVD block */
                kv_update_uvd_dpm(adev, gate);
 
-               ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                            AMD_PG_STATE_UNGATE);
+               amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                      AMD_PG_STATE_UNGATE);
        }
 }
 
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct kv_power_info *pi = kv_get_pi(adev);
-       int ret;
 
        pi->vce_power_gated = gate;
 
        if (gate) {
                /* stop the VCE block */
-               ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
-                                                            AMD_PG_STATE_GATE);
+               amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+                                                      AMD_PG_STATE_GATE);
                kv_enable_vce_dpm(adev, false);
                if (pi->caps_vce_pg) /* power off the VCE block */
                        amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
                        amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
                kv_enable_vce_dpm(adev, true);
                /* re-init the VCE block */
-               ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
-                                                            AMD_PG_STATE_UNGATE);
+               amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+                                                      AMD_PG_STATE_UNGATE);
        }
 }