return -EINVAL;
                }
 
-               ret = regmap_write(map, reg_irqclr, val_irqclr);
+               ret = regmap_update_bits(map, reg_irqclr, val_irqclr, val_irqclr);
                if (ret) {
                        dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", ret);
                        return ret;
        struct lpass_variant *v = drvdata->variant;
        irqreturn_t ret = IRQ_NONE;
        int rv;
-       unsigned int reg = 0, val = 0;
+       unsigned int reg, val, mask;
        struct regmap *map;
        unsigned int dai_id = cpu_dai->driver->id;
 
+       mask = LPAIF_IRQ_ALL(chan);
        switch (dai_id) {
        case LPASS_DP_RX:
                map = drvdata->hdmiif_map;
        return -EINVAL;
        }
        if (interrupts & LPAIF_IRQ_PER(chan)) {
-
-               rv = regmap_write(map, reg, LPAIF_IRQ_PER(chan) | val);
+               rv = regmap_update_bits(map, reg, mask, (LPAIF_IRQ_PER(chan) | val));
                if (rv) {
                        dev_err(soc_runtime->dev,
                                "error writing to irqclear reg: %d\n", rv);
        }
 
        if (interrupts & LPAIF_IRQ_XRUN(chan)) {
-               rv = regmap_write(map, reg, LPAIF_IRQ_XRUN(chan) | val);
+               rv = regmap_update_bits(map, reg, mask, (LPAIF_IRQ_XRUN(chan) | val));
                if (rv) {
                        dev_err(soc_runtime->dev,
                                "error writing to irqclear reg: %d\n", rv);
        }
 
        if (interrupts & LPAIF_IRQ_ERR(chan)) {
-               rv = regmap_write(map, reg, LPAIF_IRQ_ERR(chan) | val);
+               rv = regmap_update_bits(map, reg, mask, (LPAIF_IRQ_ERR(chan) | val));
                if (rv) {
                        dev_err(soc_runtime->dev,
                                "error writing to irqclear reg: %d\n", rv);