powerpc/perf: Use the address from SIAR register to set cpumode flags

While setting the processor mode for any sample, perf_get_misc_flags()
expects the privilege level to differentiate the userspace and kernel
address. On power10 DD1, there is an issue that causes MSR_HV MSR_PR
bits of Sampled Instruction Event Register (SIER) not to be set for
marked events. Hence add a check to use the address in SIAR (Sampled
Instruction Address Register) to identify the privilege level.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201021085329.384535-3-maddy@linux.ibm.com

diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 3b62dbb947964e186e25474cbf888eb71d69bcb0..6be0349e01ad3e49cdd9445ff955f574b367c63a 100644 (file)
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -250,10 +250,24 @@ static inline u32 perf_flags_from_msr(struct pt_regs *regs)
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
        bool use_siar = regs_use_siar(regs);
+       unsigned long mmcra = regs->dsisr;
+       int marked = mmcra & MMCRA_SAMPLE_ENABLE;
 
        if (!use_siar)
                return perf_flags_from_msr(regs);
 
+       /*
+        * Check the address in SIAR to identify the
+        * privilege levels since the SIER[MSR_HV, MSR_PR]
+        * bits are not set for marked events in power10
+        * DD1.
+        */
+       if (marked && (ppmu->flags & PPMU_P10_DD1)) {
+               if (is_kernel_addr(mfspr(SPRN_SIAR)))
+                       return PERF_RECORD_MISC_KERNEL;
+               return PERF_RECORD_MISC_USER;
+       }
+
        /*
         * If we don't have flags in MMCRA, rather than using
         * the MSR, we intuit the flags from the address in