]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/i915: pass dev_priv explicitly to TRANS_VRR_VMIN
authorJani Nikula <jani.nikula@intel.com>
Wed, 8 May 2024 15:47:49 +0000 (18:47 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 10 May 2024 08:23:47 +0000 (11:23 +0300)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VRR_VMIN register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ac1c6545a80e4cbdc98f54f8d67e69fd46cdcc91.1715183162.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_vrr.c
drivers/gpu/drm/i915/i915_reg.h

index d9024ccf6098d47e3df90ff2a680a9dab83f690a..fd0f0794f6dc4ec2af9c412169c284fa2e51a68e 100644 (file)
@@ -218,7 +218,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
                return;
        }
 
-       intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
+       intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
+                      crtc_state->vrr.vmin - 1);
        intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
                       crtc_state->vrr.vmax - 1);
        intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
@@ -312,7 +313,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
                crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
                crtc_state->vrr.vmax = intel_de_read(dev_priv,
                                                     TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1;
-               crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
+               crtc_state->vrr.vmin = intel_de_read(dev_priv,
+                                                    TRANS_VRR_VMIN(dev_priv, cpu_transcoder)) + 1;
        }
 
        if (crtc_state->vrr.enable) {
index e24a6998babd3acff4cb5ef57f83d318202ff450..90f73b5ede3a8eb4f4f71e54b53a176910a610cf 100644 (file)
 #define _TRANS_VRR_VMIN_B              0x61434
 #define _TRANS_VRR_VMIN_C              0x62434
 #define _TRANS_VRR_VMIN_D              0x63434
-#define TRANS_VRR_VMIN(trans)          _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
+#define TRANS_VRR_VMIN(dev_priv, trans)                _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
 #define   VRR_VMIN_MASK                        REG_GENMASK(15, 0)
 
 #define _TRANS_VRR_VMAXSHIFT_A         0x60428