qla27xx_get_active_image(vha, &active_regions);
        regions.global_image = active_regions.global;
 
+       if (IS_QLA27XX(ha))
+               regions.nvme_params = QLA27XX_PRIMARY_IMAGE;
+
        if (IS_QLA28XX(ha)) {
                qla28xx_get_aux_images(vha, &active_regions);
                regions.board_config = active_regions.aux.board_config;
                regions.vpd_nvram = active_regions.aux.vpd_nvram;
                regions.npiv_config_0_1 = active_regions.aux.npiv_config_0_1;
                regions.npiv_config_2_3 = active_regions.aux.npiv_config_2_3;
+               regions.nvme_params = active_regions.aux.nvme_params;
        }
 
        ql_dbg(ql_dbg_user, vha, 0x70e1,
-           "%s(%lu): FW=%u BCFG=%u VPDNVR=%u NPIV01=%u NPIV02=%u\n",
+           "%s(%lu): FW=%u BCFG=%u VPDNVR=%u NPIV01=%u NPIV02=%u NVME_PARAMS=%u\n",
            __func__, vha->host_no, regions.global_image,
            regions.board_config, regions.vpd_nvram,
-           regions.npiv_config_0_1, regions.npiv_config_2_3);
+           regions.npiv_config_0_1, regions.npiv_config_2_3, regions.nvme_params);
 
        sg_copy_from_buffer(bsg_job->reply_payload.sg_list,
            bsg_job->reply_payload.sg_cnt, ®ions, sizeof(regions));
 
        uint8_t vpd_nvram;
        uint8_t npiv_config_0_1;
        uint8_t npiv_config_2_3;
-       uint8_t reserved[32];
+       uint8_t nvme_params;
+       uint8_t reserved[31];
 } __packed;
 
 #include "qla_edif_bsg.h"
 
                uint8_t vpd_nvram;
                uint8_t npiv_config_0_1;
                uint8_t npiv_config_2_3;
+               uint8_t nvme_params;
        } aux;
 };
 
 #define QLA28XX_AUX_IMG_VPD_NVRAM              BIT_1
 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1                BIT_2
 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3                BIT_3
+#define QLA28XX_AUX_IMG_NVME_PARAMS            BIT_4
 
 #define SET_VP_IDX     1
 #define SET_AL_PA      2
 
 #define FLT_REG_VPD_SEC_27XX_1 0x52
 #define FLT_REG_VPD_SEC_27XX_2 0xD8
 #define FLT_REG_VPD_SEC_27XX_3 0xDA
+#define FLT_REG_NVME_PARAMS_27XX       0x21
 
 /* 28xx */
 #define FLT_REG_AUX_IMG_PRI_28XX       0x125
 #define FLT_REG_MPI_SEC_28XX           0xF0
 #define FLT_REG_PEP_PRI_28XX           0xD1
 #define FLT_REG_PEP_SEC_28XX           0xF1
+#define FLT_REG_NVME_PARAMS_PRI_28XX   0x14E
+#define FLT_REG_NVME_PARAMS_SEC_28XX   0x179
 
 struct qla_flt_region {
        __le16  code;
 
 
        active_regions->aux.npiv_config_2_3 =
            qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3);
+
+       active_regions->aux.nvme_params =
+           qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NVME_PARAMS);
 }
 
 static int
        }
 
        ql_dbg(ql_dbg_init, vha, 0x018f,
-           "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u\n",
+           "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u, NVME=%u\n",
            active_regions->aux.board_config,
            active_regions->aux.vpd_nvram,
            active_regions->aux.npiv_config_0_1,
-           active_regions->aux.npiv_config_2_3);
+           active_regions->aux.npiv_config_2_3,
+           active_regions->aux.nvme_params);
 }
 
 void