]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANS
authorJani Nikula <jani.nikula@intel.com>
Tue, 4 Jun 2024 15:26:23 +0000 (18:26 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 7 Jun 2024 08:31:23 +0000 (11:31 +0300)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the MTL_CLKGATE_DIS_TRANS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b330d86c5e3012513daa36dceffd2db45f0d7850.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/i915_reg.h

index 4a4124a92a0df8908778fac513ce2588a9200813..21f6a4fa86a48f12af4456f29f582206c087e33a 100644 (file)
@@ -1716,7 +1716,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
                if (!intel_dp->psr.panel_replay_enabled &&
                    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv,
-                                    MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
+                                    MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
+                                    0,
                                     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
                else if (IS_ALDERLAKE_P(dev_priv))
                        intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
@@ -1897,7 +1898,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
                if (!intel_dp->psr.panel_replay_enabled &&
                    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv,
-                                    MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
+                                    MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
                                     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
                else if (IS_ALDERLAKE_P(dev_priv))
                        intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
index 7d68f6806e5bef497fe161ee94b4fa269506618d..15ad35178f1aff23c7c210f076b858f8354f82ab 100644 (file)
@@ -4637,7 +4637,7 @@ enum skl_power_gate {
 
 #define _MTL_CLKGATE_DIS_TRANS_A                       0x604E8
 #define _MTL_CLKGATE_DIS_TRANS_B                       0x614E8
-#define MTL_CLKGATE_DIS_TRANS(trans)                   _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
+#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans)                 _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
 #define  MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS                REG_BIT(7)
 
 #define MTL_MEM_SS_INFO_GLOBAL                 _MMIO(0x45700)