ironlake_get_fdi_m_n_config(crtc, pipe_config);
 
                if (HAS_PCH_IBX(dev_priv)) {
+                       /*
+                        * The pipe->pch transcoder and pch transcoder->pll
+                        * mapping is fixed.
+                        */
                        pll_id = (enum intel_dpll_id) crtc->pipe;
                } else {
                        tmp = I915_READ(PCH_DPLL_SEL);
        enum intel_display_power_domain power_domain;
        u32 tmp;
 
+       /*
+        * The pipe->transcoder mapping is fixed with the exception of the eDP
+        * transcoder handled below.
+        */
        pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
 
        /*