mce-intel-ivb/mce-intel-sb: remove code commented with #if 0

The dead code is there for a long time without any attempts
to actually implement it for SB/IVB. As such CPUs were released
a long time ago, it is unlikely that someone would address the
comments there.

So, drop the dead code. If needed, this patch can be reversed
later.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/mce-intel-ivb.c b/mce-intel-ivb.c
index 257299e5b737ea7e9f15a14b8fe4c478c79f6af2..2aace89ffc79534f7ec6565e60201ea2cc26051c 100644 (file)
--- a/mce-intel-ivb.c
+++ b/mce-intel-ivb.c
@@ -140,30 +140,3 @@ void ivb_decode_model(struct ras_events *ras, struct mce_event *e)
        else
                mce_snprintf(e->mc_location, "rank=%d", rank1);
 }
-
-/*
- * Ivy Bridge EP and EX processors (family 6, model 62) support additional
- * logging for corrected errors in the integrated memory controller (IMC)
- * banks. The mode is off by default, but can be enabled by setting the
- * "MemError Log Enable" * bit in MSR_ERROR_CONTROL (MSR 0x17f).
- * The SDM leaves it as an exercise for the reader to convert the
- * faling rank to a DIMM slot.
- */
-#if 0
-static int failrank2dimm(unsigned int failrank, int socket, int channel)
-{
-       switch (failrank) {
-       case 0: case 1: case 2: case 3:
-               return 0;
-       case 4: case 5:
-               return 1;
-       case 6: case 7:
-               if (get_memdimm(socket, channel, 2, 0))
-                       return 2;
-               else
-                       return 1;
-       }
-       return -1;
-}
-#endif
-

diff --git a/mce-intel-sb.c b/mce-intel-sb.c
index b1db3169f346f2e5f238357e37d246f485a7343e..2d3f260cda8a813ec6ace42ee8b0f40e2a05a979 100644 (file)
--- a/mce-intel-sb.c
+++ b/mce-intel-sb.c
@@ -132,37 +132,3 @@ void snb_decode_model(struct ras_events *ras, struct mce_event *e)
        else
                mce_snprintf(e->mc_location, "rank=%d", rank1);
 }
-
-#if 0
-/*
- * Sandy Bridge EP and EP4S processors (family 6, model 45) support additional
- * logging for corrected errors in the integrated memory controller (IMC)
- * banks. The mode is off by default, but can be enabled by setting the
- * "MemError Log Enable" * bit in MSR_ERROR_CONTROL (MSR 0x17f).
- * The documentation in the August 2012 edition of Intel's Software developer
- * manual has some minor errors because the wrong version of table 16-16
- * "Intel IMC MC Error Codes for IA32_MCi_MISC (i= 8, 11)" was included.
- * Corrections are:
- *  Bit 62 is the "VALID" bit for the "first-device" bits in MISC and STATUS
- *  Bit 63 is the "VALID" bit for the "second-device" bits in MISC
- *  Bits 58:56 and 61:59 should be marked as "reserved".
- * There should also be a footnote explaining how the "failing rank" fields
- * can be converted to a DIMM number within a channel for systems with either
- * two or three DIMMs per channel.
- */
-static int failrank2dimm(unsigned int failrank, int socket, int channel)
-{
-       switch (failrank) {
-       case 0: case 1: case 2: case 3:
-               return 0;
-       case 4: case 5:
-               return 1;
-       case 6: case 7:
-               if (get_memdimm(socket, channel, 2, 0))
-                       return 2;
-               else
-                       return 1;
-       }
-       return -1;
-}
-#endif