*/
        int clk_input_pin;
 
+       /*
+        * This flag works when both clock and FS are outputs for the cpu
+        * and makes clock more accurate (FS is not symmetrical and the
+        * clock is very fast.
+        * The clock becoming faster is named
+        * i2s continuous serial clock (I2S_SCK) and it is an externally
+        * visible bit clock.
+        *
+        * first line : WordSelect
+        * second line : ContinuousSerialClock
+        * third line: SerialData
+        *
+        * SYMMETRICAL APPROACH:
+        *   _______________________          LEFT
+        * _|         RIGHT         |______________________|
+        *     _   _         _   _   _   _         _   _
+        *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
+        *     _   _         _   _   _   _         _   _
+        *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
+        *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
+        *
+        * ACCURATE CLOCK APPROACH:
+        *   ______________          LEFT
+        * _|     RIGHT    |_______________________________|
+        *     _         _   _         _   _   _   _   _   _
+        *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
+        *     _         _   _          _      dummy cycles
+        *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
+        *    \_/       \_/ \_/        \_/
+        *
+        */
+       bool i2s_accurate_sck;
+
        /* McASP specific fields */
        int tdm_slots;
        u8 op_mode;
 
        unsigned int fmt;
        int clk_div;
        int clk_input_pin;
+       bool i2s_accurate_sck;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
                       DAVINCI_MCBSP_SRGR_CLKSM;
                srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
                                                8 - 1);
-               /* symmetric waveforms */
-               clk_div = freq / (mcbsp_word_length * 16) /
-                         params->rate_num * params->rate_den;
-               srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
-                                               16 - 1);
+               if (dev->i2s_accurate_sck) {
+                       clk_div = 256;
+                       do {
+                               framesize = (freq / (--clk_div)) /
+                               params->rate_num *
+                                       params->rate_den;
+                       } while (((framesize < 33) || (framesize > 4095)) &&
+                                (clk_div));
+                       clk_div--;
+                       srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
+               } else {
+                       /* symmetric waveforms */
+                       clk_div = freq / (mcbsp_word_length * 16) /
+                                 params->rate_num * params->rate_den;
+                       srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
+                                                       16 - 1);
+               }
                clk_div &= 0xFF;
                srgr |= clk_div;
                break;
                dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
                        pdata->sram_size_capture;
                dev->clk_input_pin = pdata->clk_input_pin;
+               dev->i2s_accurate_sck = pdata->i2s_accurate_sck;
        }
        dev->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(dev->clk)) {