drm/i915: pass dev_priv explicitly to BCLRPAT

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the BCLRPAT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f04d0313032d5820a14cc504af390b4b1006fae6.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 15569cf96c9c57698ba3c9cd6005fbbdd545ec39..2660c4a53e6fa9d02a6195eb1dbf763a09954f83 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -193,7 +193,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
                adpa |= ADPA_PIPE_SEL(crtc->pipe);
 
        if (!HAS_PCH_SPLIT(dev_priv))
-               intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
+               intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
 
        switch (mode) {
        case DRM_MODE_DPMS_ON:
@@ -707,7 +707,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 
        drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
 
-       save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
+       save_bclrpat = intel_de_read(dev_priv,
+                                    BCLRPAT(dev_priv, cpu_transcoder));
        save_vtotal = intel_de_read(dev_priv,
                                    TRANS_VTOTAL(dev_priv, cpu_transcoder));
        vblank = intel_de_read(dev_priv,
@@ -720,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
        vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
 
        /* Set the border color to purple. */
-       intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
+       intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
 
        if (DISPLAY_VER(dev_priv) != 2) {
                u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
@@ -800,7 +801,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
        }
 
        /* Restore previous settings */
-       intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat);
+       intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
+                      save_bclrpat);
 
        return status;
 }

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 776e4450e4afa0d39c91a29afaa6c96d7a30cc8a..49f7ac0f79979167be975cb2fdc035f954eb5a63 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1870,7 +1870,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 
        /* Border color in case we don't scale up to the full screen. Black by
         * default, change to something else for debugging. */
-       intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
+       intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
 }
 
 /* Prefer intel_encoder_is_combo() */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f87fb2d015ea9d1f4cf4ebf010ce3fdfa35153b..39f92739b8225aca8cafa41d9318c86bee6b4174 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1142,7 +1142,7 @@
 #define TRANS_VTOTAL(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
 #define TRANS_VBLANK(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(dev_priv, trans)   _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
-#define BCLRPAT(trans)         _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
+#define BCLRPAT(dev_priv, trans)               _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
 #define TRANS_VSYNCSHIFT(trans)        _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
 #define PIPESRC(pipe)          _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
 #define TRANS_MULT(trans)      _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index e618a16eafac54558c567dfb2fb669ffa7450185..5e1ef52922cca993fed104131a181befbf869c75 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -237,7 +237,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
-       MMIO_D(BCLRPAT(TRANSCODER_A));
+       MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
        MMIO_D(PIPESRC(TRANSCODER_A));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
@@ -246,7 +246,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
-       MMIO_D(BCLRPAT(TRANSCODER_B));
+       MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
        MMIO_D(PIPESRC(TRANSCODER_B));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
@@ -255,7 +255,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
-       MMIO_D(BCLRPAT(TRANSCODER_C));
+       MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
        MMIO_D(PIPESRC(TRANSCODER_C));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
@@ -264,7 +264,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
-       MMIO_D(BCLRPAT(TRANSCODER_EDP));
+       MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
        MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
        MMIO_D(PIPE_DATA_N1(TRANSCODER_A));