struct vsc8531_private *vsc8531 = phydev->priv;
        u16 val, addr;
 
-       mutex_lock(&phydev->mdio.bus->mdio_lock);
+       phy_lock_mdio_bus(phydev);
        __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
 
        addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
        val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
 
        __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
-       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+       phy_unlock_mdio_bus(phydev);
 
        /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
         * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
 
        phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 
-       mutex_lock(&phydev->mdio.bus->mdio_lock);
+       phy_lock_mdio_bus(phydev);
 
        /* Some parts of the init sequence are identical for every PHY in the
         * package. Some parts are modifying the GPIO register bank which is a
        if (ret)
                goto err;
 
-       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+       phy_unlock_mdio_bus(phydev);
 
        ret = vsc8584_macsec_init(phydev);
        if (ret)
        return 0;
 
 err:
-       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+       phy_unlock_mdio_bus(phydev);
        return ret;
 }
 
 
        phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 
-       mutex_lock(&phydev->mdio.bus->mdio_lock);
+       phy_lock_mdio_bus(phydev);
 
        /* Some parts of the init sequence are identical for every PHY in the
         * package. Some parts are modifying the GPIO register bank which is a
                reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
                                                PHY_S6G_PLL_STATUS);
                if (reg == 0xffffffff) {
-                       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+                       phy_unlock_mdio_bus(phydev);
                        return -EIO;
                }
 
        } while (time_before(jiffies, deadline) && (reg & BIT(12)));
 
        if (reg & BIT(12)) {
-               mutex_unlock(&phydev->mdio.bus->mdio_lock);
+               phy_unlock_mdio_bus(phydev);
                return -ETIMEDOUT;
        }
 
                reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
                                                PHY_S6G_IB_STATUS0);
                if (reg == 0xffffffff) {
-                       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+                       phy_unlock_mdio_bus(phydev);
                        return -EIO;
                }
 
        } while (time_before(jiffies, deadline) && !(reg & BIT(8)));
 
        if (!(reg & BIT(8))) {
-               mutex_unlock(&phydev->mdio.bus->mdio_lock);
+               phy_unlock_mdio_bus(phydev);
                return -ETIMEDOUT;
        }
 
-       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+       phy_unlock_mdio_bus(phydev);
 
        ret = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 
        return ret;
 
 err:
-       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+       phy_unlock_mdio_bus(phydev);
        return ret;
 }
 
 
                break;
        }
 
-       mutex_lock(&phydev->mdio.bus->mdio_lock);
+       phy_lock_mdio_bus(phydev);
 
        phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588);
 
 
        phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 
-       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+       phy_unlock_mdio_bus(phydev);
 
        return val;
 }
                break;
        }
 
-       mutex_lock(&phydev->mdio.bus->mdio_lock);
+       phy_lock_mdio_bus(phydev);
 
        bypass = phy_ts_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
 
        if (cond && upper)
                phy_ts_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, bypass);
 
-       mutex_unlock(&phydev->mdio.bus->mdio_lock);
+       phy_unlock_mdio_bus(phydev);
 }
 
 /* Pick bytes from PTP header */
        u32 val;
 
        if (!vsc8584_is_1588_input_clk_configured(phydev)) {
-               mutex_lock(&phydev->mdio.bus->mdio_lock);
+               phy_lock_mdio_bus(phydev);
 
                /* 1588_DIFF_INPUT_CLK configuration: Use an external clock for
                 * the LTC, as per 3.13.29 in the VSC8584 datasheet.
                phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
                                  MSCC_PHY_PAGE_STANDARD);
 
-               mutex_unlock(&phydev->mdio.bus->mdio_lock);
+               phy_unlock_mdio_bus(phydev);
 
                vsc8584_set_input_clk_configured(phydev);
        }