/* Setting AVIC backing page address in the phy APIC ID table */
        new_entry = avic_get_backing_page_address(svm) |
                    AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
+       svm->avic_physical_id_entry = new_entry;
+
+       /*
+        * Initialize the real table, as vCPUs must have a valid entry in order
+        * for broadcast IPIs to function correctly (broadcast IPIs ignore
+        * invalid entries, i.e. aren't guaranteed to generate a VM-Exit).
+        */
        WRITE_ONCE(kvm_svm->avic_physical_id_table[id], new_entry);
 
        return 0;
                           struct amd_iommu_pi_data *pi)
 {
        struct kvm_vcpu *vcpu = &svm->vcpu;
-       struct kvm *kvm = vcpu->kvm;
-       struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
        unsigned long flags;
        u64 entry;
 
         * will update the pCPU info when the vCPU awkened and/or scheduled in.
         * See also avic_vcpu_load().
         */
-       entry = READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]);
+       entry = svm->avic_physical_id_entry;
        if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
                amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK,
                                    true, pi->ir_data);
         */
        spin_lock_irqsave(&svm->ir_list_lock, flags);
 
-       entry = READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]);
+       entry = svm->avic_physical_id_entry;
        WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 
        entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
        entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
        entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
 
+       svm->avic_physical_id_entry = entry;
+
+       /*
+        * If IPI virtualization is disabled, clear IsRunning when updating the
+        * actual Physical ID table, so that the CPU never sees IsRunning=1.
+        * Keep the APIC ID up-to-date in the entry to minimize the chances of
+        * things going sideways if hardware peeks at the ID.
+        */
+       if (!enable_ipiv)
+               entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
+
        WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry);
+
        avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true);
 
        spin_unlock_irqrestore(&svm->ir_list_lock, flags);
         * can't be scheduled out and thus avic_vcpu_{put,load}() can't run
         * recursively.
         */
-       entry = READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]);
+       entry = svm->avic_physical_id_entry;
 
        /* Nothing to do if IsRunning == '0' due to vCPU blocking. */
        if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK))
        avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
 
        entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
-       WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry);
+       svm->avic_physical_id_entry = entry;
+
+       if (enable_ipiv)
+               WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry);
 
        spin_unlock_irqrestore(&svm->ir_list_lock, flags);
 
 
        u32 ldr_reg;
        u32 dfr_reg;
 
+       /* This is essentially a shadow of the vCPU's actual entry in the
+        * Physical ID table that is programmed into the VMCB, i.e. that is
+        * seen by the CPU.  If IPI virtualization is disabled, IsRunning is
+        * only ever set in the shadow, i.e. is never propagated to the "real"
+        * table, so that hardware never sees IsRunning=1.
+        */
+       u64 avic_physical_id_entry;
+
        /*
         * Per-vCPU list of irqfds that are eligible to post IRQs directly to
         * the vCPU (a.k.a. device posted IRQs, a.k.a. IRQ bypass).  The list