clk: rockchip: fix mmc get phase

If the mmc clock has no rate, it can be assumed to be constant.
In such case, there is no measurable phase shift. Just return 0
in this case instead of returning an error.

Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration")
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
index 4abe7ff31f535f282127d4ead002e09c8d9751ef..975454a3dd72b3fd46681aba98061c7c42cc1952 100644 (file)
--- a/drivers/clk/rockchip/clk-mmc-phase.c
+++ b/drivers/clk/rockchip/clk-mmc-phase.c
@@ -51,9 +51,9 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
        u16 degrees;
        u32 delay_num = 0;
 
-       /* See the comment for rockchip_mmc_set_phase below */
+       /* Constant signal, no measurable phase shift */
        if (!rate)
-               return -EINVAL;
+               return 0;
 
        raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);