Blackfin: cpufreq: use a constant latency

PLL_LOCKCNT applies only to the PLL programming sequence which does not
apply to core and system clock dividers.  Writes to PLL_DIV to change the
CSEL/SSEL dividers take effect immediately.

There is still overhead in software in writing the new dividers, so just
use a value of 50us as this should be good enough.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 01506504e6d05cb464234febd43dabddf66e420e..3d18d2ba47867e835095696543b8d614243fbb3b 100644 (file)
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -138,7 +138,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
                                                 dpm_state_table[index].tscale);
        }
 
-       policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
+       policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
+
        /*Now ,only support one cpu */
        policy->cur = cclk;
        cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);