#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
 
 struct chip_data {
-       u32 mcr_val;
        u32 ctar_val;
        u16 void_write_data;
 };
                else
                        dspi->bytes_per_word = 2;
 
-               regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
                regmap_update_bits(dspi->regmap, SPI_MCR,
-                               SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
-                               SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
+                                  SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
+                                  SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
                regmap_write(dspi->regmap, SPI_CTAR(0),
                             dspi->cur_chip->ctar_val |
                             SPI_FRAME_BITS(transfer->bits_per_word));
                sck_cs_delay = pdata->sck_cs_delay;
        }
 
-       chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
-               SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
-
        chip->void_write_data = 0;
 
        clkrate = clk_get_rate(dspi->clk);
 
 static void dspi_init(struct fsl_dspi *dspi)
 {
+       regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS);
        regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
 }