if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
            (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)) {
                bo_va->is_xgmi = true;
-               mutex_lock(&adev->vm_manager.lock_pstate);
                /* Power up XGMI if it can be potentially used */
-               if (++adev->vm_manager.xgmi_map_counter == 1)
-                       amdgpu_xgmi_set_pstate(adev, 1);
-               mutex_unlock(&adev->vm_manager.lock_pstate);
+               amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
        }
 
        return bo_va;
 
        dma_fence_put(bo_va->last_pt_update);
 
-       if (bo && bo_va->is_xgmi) {
-               mutex_lock(&adev->vm_manager.lock_pstate);
-               if (--adev->vm_manager.xgmi_map_counter == 0)
-                       amdgpu_xgmi_set_pstate(adev, 0);
-               mutex_unlock(&adev->vm_manager.lock_pstate);
-       }
+       if (bo && bo_va->is_xgmi)
+               amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
 
        kfree(bo_va);
 }
 
        idr_init(&adev->vm_manager.pasid_idr);
        spin_lock_init(&adev->vm_manager.pasid_lock);
-
-       adev->vm_manager.xgmi_map_counter = 0;
-       mutex_init(&adev->vm_manager.lock_pstate);
 }
 
 /**
 
 
        if (lock)
                mutex_lock(&tmp->hive_lock);
-       tmp->pstate = -1;
+       tmp->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
+       tmp->hi_req_gpu = NULL;
+       /*
+        * hive pstate on boot is high in vega20 so we have to go to low
+        * pstate on after boot.
+        */
+       tmp->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
        mutex_unlock(&xgmi_mutex);
 
        return tmp;
 {
        int ret = 0;
        struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
-       struct amdgpu_device *tmp_adev;
-       bool update_hive_pstate = true;
-       bool is_high_pstate = pstate && adev->asic_type == CHIP_VEGA20;
+       struct amdgpu_device *request_adev = hive->hi_req_gpu ?
+                                               hive->hi_req_gpu : adev;
+       bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
+       bool init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
 
-       if (!hive)
+       /* fw bug so temporarily disable pstate switching */
+       if (!hive || adev->asic_type == CHIP_VEGA20)
                return 0;
 
        mutex_lock(&hive->hive_lock);
 
-       if (hive->pstate == pstate) {
-               adev->pstate = is_high_pstate ? pstate : adev->pstate;
+       if (is_hi_req)
+               hive->hi_req_count++;
+       else
+               hive->hi_req_count--;
+
+       /*
+        * Vega20 only needs single peer to request pstate high for the hive to
+        * go high but all peers must request pstate low for the hive to go low
+        */
+       if (hive->pstate == pstate ||
+                       (!is_hi_req && hive->hi_req_count && !init_low))
                goto out;
-       }
 
-       dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
+       dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
 
-       ret = amdgpu_dpm_set_xgmi_pstate(adev, pstate);
+       ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
        if (ret) {
-               dev_err(adev->dev,
+               dev_err(request_adev->dev,
                        "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
-                       adev->gmc.xgmi.node_id,
-                       adev->gmc.xgmi.hive_id, ret);
+                       request_adev->gmc.xgmi.node_id,
+                       request_adev->gmc.xgmi.hive_id, ret);
                goto out;
        }
 
-       /* Update device pstate */
-       adev->pstate = pstate;
-
-       /*
-        * Update the hive pstate only all devices of the hive
-        * are in the same pstate
-        */
-       list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
-               if (tmp_adev->pstate != adev->pstate) {
-                       update_hive_pstate = false;
-                       break;
-               }
-       }
-       if (update_hive_pstate || is_high_pstate)
+       if (init_low)
+               hive->pstate = hive->hi_req_count ?
+                                       hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
+       else {
                hive->pstate = pstate;
-
+               hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
+                                                       adev : NULL;
+       }
 out:
        mutex_unlock(&hive->hive_lock);
-
        return ret;
 }
 
                goto exit;
        }
 
-       /* Set default device pstate */
-       adev->pstate = -1;
-
        top_info = &adev->psp.xgmi_context.top_info;
 
        list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
 
 #include <drm/task_barrier.h>
 #include "amdgpu_psp.h"
 
+
 struct amdgpu_hive_info {
        uint64_t                hive_id;
        struct list_head        device_list;
        struct kobject *kobj;
        struct device_attribute dev_attr;
        struct amdgpu_device *adev;
-       int pstate; /*0 -- low , 1 -- high , -1 unknown*/
+       int hi_req_count;
+       struct amdgpu_device *hi_req_gpu;
        struct task_barrier tb;
+       enum {
+               AMDGPU_XGMI_PSTATE_MIN,
+               AMDGPU_XGMI_PSTATE_MAX_VEGA20,
+               AMDGPU_XGMI_PSTATE_UNKNOWN
+       } pstate;
 };
 
 struct amdgpu_pcs_ras_field {