yesno(intel_dp_source_supports_hbr2(intel_dp)),
                      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
-       /* Set the max lane count for sink */
-       intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+       if (intel_dp->reset_link_params) {
+               /* Set the max lane count for sink */
+               intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 
-       /* Set the max link BW for sink */
-       intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
+               /* Set the max link BW for sink */
+               intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
+
+               intel_dp->reset_link_params = false;
+       }
 
        intel_dp_print_rates(intel_dp);
 
        if (lspcon->active)
                lspcon_resume(lspcon);
 
+       intel_dp->reset_link_params = true;
+
        pps_lock(intel_dp);
 
        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                      long_hpd ? "long" : "short");
 
        if (long_hpd) {
+               intel_dp->reset_link_params = true;
                intel_dp->detect_done = false;
                return IRQ_NONE;
        }
                 intel_dig_port->max_lanes, port_name(port)))
                return false;
 
+       intel_dp->reset_link_params = true;
        intel_dp->pps_pipe = INVALID_PIPE;
        intel_dp->active_pipe = INVALID_PIPE;