uint32_t        eng_distance;
        uint32_t        eng_addr_distance; /* include LO32/HI32 */
 
+       uint32_t        vm_cntx_cntl;
        uint32_t        vm_cntx_cntl_vm_fault;
        uint32_t        vm_l2_bank_select_reserved_cid2;
 
 
                                    i * hub->ctx_addr_distance,
                                    upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
+
+       hub->vm_cntx_cntl = tmp;
 }
 
 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 
                                    i * hub->ctx_addr_distance,
                                    upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
+
+       hub->vm_cntx_cntl = tmp;
 }
 
 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
 
                                    i * hub->ctx_addr_distance,
                                    upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
+
+       hub->vm_cntx_cntl = tmp;
 }
 
 static void gfxhub_v3_0_program_invalidation(struct amdgpu_device *adev)
 
                                    i * hub->ctx_addr_distance,
                                    upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
+
+       hub->vm_cntx_cntl = tmp;
 }
 
 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 
                                    i * hub->ctx_addr_distance,
                                    upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
+
+       hub->vm_cntx_cntl = tmp;
 }
 
 static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev)
 
                                    i * hub->ctx_addr_distance,
                                    upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
+
+       hub->vm_cntx_cntl = tmp;
 }
 
 static void mmhub_v3_0_program_invalidation(struct amdgpu_device *adev)