enetc: Set MDIO_CFG_HOLD to the recommended value of 2

This increases the MDIO hold time to 5 enet_clk cycles from the previous
value of 0. This is actually the out-of-reset value, that the driver was
previously overwriting with 0. Zero worked for the external MDIO, but
breaks communication with the internal MDIO buses on which the PCS of
ENETC SI's and Felix switch are found.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
index 18c68e048d43a4cf79ffc5ba89af091a71127fd4..48c32a171afa67d8ce87dbab99607fe64e4f3507 100644 (file)
--- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
@@ -31,15 +31,19 @@ static inline void _enetc_mdio_wr(struct enetc_mdio_priv *mdio_priv, int off,
        _enetc_mdio_wr(mdio_priv, ENETC_##off, val)
 #define enetc_mdio_rd_reg(off) enetc_mdio_rd(mdio_priv, off)
 
-#define ENETC_MDC_DIV          258
-
 #define MDIO_CFG_CLKDIV(x)     ((((x) >> 1) & 0xff) << 8)
 #define MDIO_CFG_BSY           BIT(0)
 #define MDIO_CFG_RD_ER         BIT(1)
+#define MDIO_CFG_HOLD(x)       (((x) << 2) & GENMASK(4, 2))
 #define MDIO_CFG_ENC45         BIT(6)
  /* external MDIO only - driven on neg MDC edge */
 #define MDIO_CFG_NEG           BIT(23)
 
+#define ENETC_EMDIO_CFG \
+       (MDIO_CFG_HOLD(2) | \
+        MDIO_CFG_CLKDIV(258) | \
+        MDIO_CFG_NEG)
+
 #define MDIO_CTL_DEV_ADDR(x)   ((x) & 0x1f)
 #define MDIO_CTL_PORT_ADDR(x)  (((x) & 0x1f) << 5)
 #define MDIO_CTL_READ          BIT(15)
@@ -61,7 +65,7 @@ int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
        u16 dev_addr;
        int ret;
 
-       mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
+       mdio_cfg = ENETC_EMDIO_CFG;
        if (regnum & MII_ADDR_C45) {
                dev_addr = (regnum >> 16) & 0x1f;
                mdio_cfg |= MDIO_CFG_ENC45;
@@ -108,7 +112,7 @@ int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
        u16 dev_addr, value;
        int ret;
 
-       mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
+       mdio_cfg = ENETC_EMDIO_CFG;
        if (regnum & MII_ADDR_C45) {
                dev_addr = (regnum >> 16) & 0x1f;
                mdio_cfg |= MDIO_CFG_ENC45;