arm64: Fix usage of new shifted MDCR_EL2 values

Since the linked fixes commit, these masks are already shifted so remove
the shifts. One issue that this fixes is SPE and TRBE not being
available anymore:

 arm_spe_pmu arm,spe-v1: profiling buffer owned by higher exception level

Fixes: 641630313e9c ("arm64: sysreg: Migrate MDCR_EL2 definition to table")
Signed-off-by: James Clark <james.clark@linaro.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241122164636.2944180-1-james.clark@linaro.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 4cd41464be3f25e271c4ba808d5f4f77ef48ee82..f134907d3c087aad9d56fa0ca5a4c11ae12a3df1 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -79,7 +79,7 @@
                      1 << PMSCR_EL2_PA_SHIFT)
        msr_s   SYS_PMSCR_EL2, x0               // addresses and physical counter
 .Lskip_spe_el2_\@:
-       mov     x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
+       mov     x0, #MDCR_EL2_E2PB_MASK
        orr     x2, x2, x0                      // If we don't have VHE, then
                                                // use EL1&0 translation.
 
@@ -92,7 +92,7 @@
        and     x0, x0, TRBIDR_EL1_P
        cbnz    x0, .Lskip_trace_\@             // If TRBE is available at EL2
 
-       mov     x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
+       mov     x0, #MDCR_EL2_E2TB_MASK
        orr     x2, x2, x0                      // allow the EL1&0 translation
                                                // to own it.
 

diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index 65f76064c86b24db53795ea420efe56f4a21172d..ae990da1eae5a97221b87fdd4b839eccfeaa125c 100644 (file)
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -114,8 +114,8 @@ SYM_CODE_START_LOCAL(__finalise_el2)
 
        // Use EL2 translations for SPE & TRBE and disable access from EL1
        mrs     x0, mdcr_el2
-       bic     x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
-       bic     x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
+       bic     x0, x0, #MDCR_EL2_E2PB_MASK
+       bic     x0, x0, #MDCR_EL2_E2TB_MASK
        msr     mdcr_el2, x0
 
        // Transfer the MM state from EL1 to EL2

diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
index 01616c39a810777a123b6a3a5da33a16b6768ad7..071993c16de81ca0b0181c56d0598b1b026ae018 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
+++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
@@ -126,7 +126,7 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
        /* Trap SPE */
        if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) {
                mdcr_set |= MDCR_EL2_TPMS;
-               mdcr_clear |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
+               mdcr_clear |= MDCR_EL2_E2PB_MASK;
        }
 
        /* Trap Trace Filter */
@@ -143,7 +143,7 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
 
        /* Trap External Trace */
        if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_ExtTrcBuff), feature_ids))
-               mdcr_clear |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT;
+               mdcr_clear |= MDCR_EL2_E2TB_MASK;
 
        vcpu->arch.mdcr_el2 |= mdcr_set;
        vcpu->arch.mdcr_el2 &= ~mdcr_clear;