return val;
 }
 
-static void
+static int
 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
 {
        struct mii_bus *bus = priv->bus;
 
 exit:
        mutex_unlock(&bus->mdio_lock);
+       return ret;
 }
 
 static u32
 {
        struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 
-       qca8k_write(priv, reg, val);
-
-       return 0;
+       return qca8k_write(priv, reg, val);
 }
 
 static const struct regmap_range qca8k_readable_ranges[] = {
 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
 {
        u32 reg;
+       int ret;
 
        /* Set the command and FDB index */
        reg = QCA8K_ATU_FUNC_BUSY;
        }
 
        /* Write the function register triggering the table access */
-       qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
+       ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
+       if (ret)
+               return ret;
 
        /* wait for completion */
        if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
 qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
 {
        u32 reg;
+       int ret;
 
        /* Set the command and VLAN index */
        reg = QCA8K_VTU_FUNC1_BUSY;
        reg |= vid << QCA8K_VTU_FUNC1_VID_S;
 
        /* Write the function register triggering the table access */
-       qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
+       ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
+       if (ret)
+               return ret;
 
        /* wait for completion */
        if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY))
                reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
                                QCA8K_VTU_FUNC0_EG_MODE_S(port);
 
-       qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
+       ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
+       if (ret)
+               return ret;
        ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 
 out:
        if (del) {
                ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
        } else {
-               qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
+               ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
+               if (ret)
+                       return ret;
                ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
        }
 
        return ret;
 }
 
-static void
+static int
 qca8k_mib_init(struct qca8k_priv *priv)
 {
+       int ret;
+
        mutex_lock(&priv->reg_mutex);
        qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
        qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
        qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
-       qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
+
+       ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
+
        mutex_unlock(&priv->reg_mutex);
+       return ret;
 }
 
 static void
 qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
 {
        u32 phy, val;
+       int ret;
 
        if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
                return -EINVAL;
              QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
              QCA8K_MDIO_MASTER_DATA(data);
 
-       qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
+       ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
+       if (ret)
+               return ret;
 
        return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
                QCA8K_MDIO_MASTER_BUSY);
 qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
 {
        u32 phy, val;
+       int ret;
 
        if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
                return -EINVAL;
              QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
              QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 
-       qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
+       ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
+       if (ret)
+               return ret;
 
        if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
                            QCA8K_MDIO_MASTER_BUSY))
                      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
 
        /* Enable MIB counters */
-       qca8k_mib_init(priv);
+       ret = qca8k_mib_init(priv);
+       if (ret)
+               dev_warn(priv->dev, "mib init failed");
 
        /* Enable QCA header mode on the cpu port */
-       qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
-                   QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
-                   QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
+       ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
+                         QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
+                         QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
+       if (ret) {
+               dev_err(priv->dev, "failed enabling QCA header mode");
+               return ret;
+       }
 
        /* Disable forwarding by default on all ports */
        for (i = 0; i < QCA8K_NUM_PORTS; i++)
                qca8k_port_set_status(priv, i, 0);
 
        /* Forward all unknown frames to CPU port for Linux processing */
-       qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
-                   BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
-                   BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
-                   BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
-                   BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
+       ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
+                         BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
+                         BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
+                         BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
+                         BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
+       if (ret)
+               return ret;
 
        /* Setup connection between CPU port & user ports */
        for (i = 0; i < QCA8K_NUM_PORTS; i++) {
                        qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
                                  0xfff << shift,
                                  QCA8K_PORT_VID_DEF << shift);
-                       qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
-                                   QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
-                                   QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
+                       ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
+                                         QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
+                                         QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
+                       if (ret)
+                               return ret;
                }
        }
 
        /* Setup our port MTUs to match power on defaults */
        for (i = 0; i < QCA8K_NUM_PORTS; i++)
                priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
-       qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
+       ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
+       if (ret)
+               dev_warn(priv->dev, "failed setting MTU settings");
 
        /* Flush the FDB table */
        qca8k_fdb_flush(priv);
 {
        struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
        u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
-       int ret = 0;
        u32 reg;
+       int ret;
 
        mutex_lock(&priv->reg_mutex);
        reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
                reg |= lpi_en;
        else
                reg &= ~lpi_en;
-       qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
+       ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
 
 exit:
        mutex_unlock(&priv->reg_mutex);
                        mtu = priv->port_mtu[i];
 
        /* Include L2 header / FCS length */
-       qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
-
-       return 0;
+       return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
 }
 
 static int
        bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
        bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
        struct qca8k_priv *priv = ds->priv;
-       int ret = 0;
+       int ret;
 
        ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
        if (ret) {
 
                qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
                          0xfff << shift, vlan->vid << shift);
-               qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
-                           QCA8K_PORT_VLAN_CVID(vlan->vid) |
-                           QCA8K_PORT_VLAN_SVID(vlan->vid));
+               ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
+                                 QCA8K_PORT_VLAN_CVID(vlan->vid) |
+                                 QCA8K_PORT_VLAN_SVID(vlan->vid));
+               if (ret)
+                       return ret;
        }
 
        return 0;
                    const struct switchdev_obj_port_vlan *vlan)
 {
        struct qca8k_priv *priv = ds->priv;
-       int ret = 0;
+       int ret;
 
        ret = qca8k_vlan_del(priv, port, vlan->vid);
        if (ret)