x86/msr: Rename 'rdmsrl_on_cpu()' to 'rdmsrq_on_cpu()'

Suggested-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Juergen Gross <jgross@suse.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Xin Li <xin@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 756dd11742ad272b78a0856f19da9fbb1d552d12..dd53dd87cdec9c9e905f12b93c840965953a1f5a 100644 (file)
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -3765,7 +3765,7 @@ static int skx_msr_cpu_bus_read(int cpu, u64 *topology)
 {
        u64 msr_value;
 
-       if (rdmsrl_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) ||
+       if (rdmsrq_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) ||
                        !(msr_value & SKX_MSR_CPU_BUS_VALID_BIT))
                return -ENXIO;
 

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 52983279c953f497592f3b3ed293a4f531a88578..850793b381c61a5d2a7b9a2bc29ac2be8cc03ecb 100644 (file)
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -329,7 +329,7 @@ int msr_clear_bit(u32 msr, u8 bit);
 #ifdef CONFIG_SMP
 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
+int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs);
 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs);
@@ -350,7 +350,7 @@ static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
        wrmsr(msr_no, l, h);
        return 0;
 }
-static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
+static inline int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
 {
        rdmsrq(msr_no, *q);
        return 0;

diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c
index 01d81b78d09ebcae8a1cfd0f9702d707ad3f1a4d..54236defb66698aa392bbfc33f5a079c0377d624 100644 (file)
--- a/arch/x86/kernel/cpu/intel_epb.c
+++ b/arch/x86/kernel/cpu/intel_epb.c
@@ -135,7 +135,7 @@ static ssize_t energy_perf_bias_show(struct device *dev,
        u64 epb;
        int ret;
 
-       ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
+       ret = rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
        if (ret < 0)
                return ret;
 
@@ -157,7 +157,7 @@ static ssize_t energy_perf_bias_store(struct device *dev,
        else if (kstrtou64(buf, 0, &val) || val > MAX_EPB)
                return -EINVAL;
 
-       ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
+       ret = rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
        if (ret < 0)
                return ret;
 

diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 5226f8f7fc98c4b47716b52ab63474d1a2d823ce..338aeee95bd24b0cb30ebf04d8de3e0b189e60e6 100644 (file)
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -589,7 +589,7 @@ static int inj_bank_set(void *data, u64 val)
        u64 cap;
 
        /* Get bank count on target CPU so we can handle non-uniform values. */
-       rdmsrl_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap);
+       rdmsrq_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap);
        n_banks = cap & MCG_BANKCNT_MASK;
 
        if (val >= n_banks) {
@@ -613,7 +613,7 @@ static int inj_bank_set(void *data, u64 val)
        if (cpu_feature_enabled(X86_FEATURE_SMCA)) {
                u64 ipid;
 
-               if (rdmsrl_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) {
+               if (rdmsrq_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) {
                        pr_err("Error reading IPID on CPU%d\n", m->extcpu);
                        return -EINVAL;
                }

diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c
index 434fdc21a86e17a8c11789c5ef59a4cbbb06e0d9..b6081fc2217f4a49bab897b82f14b086f9cd2e55 100644 (file)
--- a/arch/x86/lib/msr-smp.c
+++ b/arch/x86/lib/msr-smp.c
@@ -47,7 +47,7 @@ int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 }
 EXPORT_SYMBOL(rdmsr_on_cpu);
 
-int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
+int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
 {
        int err;
        struct msr_info rv;
@@ -60,7 +60,7 @@ int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
 
        return err;
 }
-EXPORT_SYMBOL(rdmsrl_on_cpu);
+EXPORT_SYMBOL(rdmsrq_on_cpu);
 
 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {

diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index d19867cf816af26fdc1a0fd7a1d04f2e6a1fbee1..8bc08f3b0d5dcd062c629233b76250a720081b81 100644 (file)
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -79,11 +79,11 @@ static bool boost_state(unsigned int cpu)
        case X86_VENDOR_INTEL:
        case X86_VENDOR_CENTAUR:
        case X86_VENDOR_ZHAOXIN:
-               rdmsrl_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr);
+               rdmsrq_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr);
                return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
        case X86_VENDOR_HYGON:
        case X86_VENDOR_AMD:
-               rdmsrl_on_cpu(cpu, MSR_K7_HWCR, &msr);
+               rdmsrq_on_cpu(cpu, MSR_K7_HWCR, &msr);
                return !(msr & MSR_K7_HWCR_CPB_DIS);
        }
        return false;

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 0615c73306cffc5058f56949e0df9bc0b20fca81..e987486cbb345750a0e44ec536109431fd7f0a4b 100644 (file)
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -197,7 +197,7 @@ static u8 msr_get_epp(struct amd_cpudata *cpudata)
        u64 value;
        int ret;
 
-       ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
+       ret = rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
        if (ret < 0) {
                pr_debug("Could not retrieve energy perf value (%d)\n", ret);
                return ret;
@@ -769,7 +769,7 @@ static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata)
                goto exit_err;
        }
 
-       ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val);
+       ret = rdmsrq_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val);
        if (ret) {
                pr_err_once("failed to read initial CPU boost state!\n");
                ret = -EIO;
@@ -1491,7 +1491,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
        }
 
        if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
-               ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
+               ret = rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
                if (ret)
                        return ret;
                WRITE_ONCE(cpudata->cppc_req_cached, value);

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 6f6c14e31795f496effea21ab9003aff35af8d3f..8ce9d54ea32ea2a01eb590ec7f12c64c2a4bc7fc 100644 (file)
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -620,7 +620,7 @@ static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
        if (!boot_cpu_has(X86_FEATURE_EPB))
                return -ENXIO;
 
-       ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
+       ret = rdmsrq_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
        if (ret)
                return (s16)ret;
 
@@ -637,7 +637,7 @@ static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
                 * MSR_HWP_REQUEST, so need to read and get EPP.
                 */
                if (!hwp_req_data) {
-                       epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
+                       epp = rdmsrq_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
                                            &hwp_req_data);
                        if (epp)
                                return epp;
@@ -659,7 +659,7 @@ static int intel_pstate_set_epb(int cpu, s16 pref)
        if (!boot_cpu_has(X86_FEATURE_EPB))
                return -ENXIO;
 
-       ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
+       ret = rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
        if (ret)
                return ret;
 
@@ -916,7 +916,7 @@ static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
        if (ratio <= 0) {
                u64 cap;
 
-               rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
+               rdmsrq_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
                ratio = HWP_GUARANTEED_PERF(cap);
        }
 
@@ -1088,7 +1088,7 @@ static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
 {
        u64 cap;
 
-       rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
+       rdmsrq_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
        WRITE_ONCE(cpu->hwp_cap_cached, cap);
        cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
        cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
@@ -1162,7 +1162,7 @@ static void intel_pstate_hwp_set(unsigned int cpu)
        if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
                min = max;
 
-       rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
+       rdmsrq_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 
        value &= ~HWP_MIN_PERF(~0L);
        value |= HWP_MIN_PERF(min);
@@ -2084,7 +2084,7 @@ static int core_get_min_pstate(int cpu)
 {
        u64 value;
 
-       rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
+       rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
        return (value >> 40) & 0xFF;
 }
 
@@ -2092,7 +2092,7 @@ static int core_get_max_pstate_physical(int cpu)
 {
        u64 value;
 
-       rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
+       rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
        return (value >> 8) & 0xFF;
 }
 
@@ -2137,7 +2137,7 @@ static int core_get_max_pstate(int cpu)
        int tdp_ratio;
        int err;
 
-       rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
+       rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
        max_pstate = (plat_info >> 8) & 0xFF;
 
        tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
@@ -2169,7 +2169,7 @@ static int core_get_turbo_pstate(int cpu)
        u64 value;
        int nont, ret;
 
-       rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
+       rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
        nont = core_get_max_pstate(cpu);
        ret = (value) & 255;
        if (ret <= nont)
@@ -2198,7 +2198,7 @@ static int knl_get_turbo_pstate(int cpu)
        u64 value;
        int nont, ret;
 
-       rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
+       rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
        nont = core_get_max_pstate(cpu);
        ret = (((value) >> 8) & 0xFF);
        if (ret <= nont)
@@ -3256,7 +3256,7 @@ static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
 
                intel_pstate_get_hwp_cap(cpu);
 
-               rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
+               rdmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
                WRITE_ONCE(cpu->hwp_req_cached, value);
 
                cpu->epp_cached = intel_pstate_get_epp(cpu, value);

diff --git a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c
index 40bbf8e45fa4bb2e6bbba825897c1d75bb68bdef..5295cd1483f4f99640296ebc17c276aed4a21cfd 100644 (file)
--- a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c
+++ b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c
@@ -51,7 +51,7 @@ static int uncore_read_control_freq(struct uncore_data *data, unsigned int *valu
        if (data->control_cpu < 0)
                return -ENXIO;
 
-       ret = rdmsrl_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap);
+       ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap);
        if (ret)
                return ret;
 
@@ -76,7 +76,7 @@ static int uncore_write_control_freq(struct uncore_data *data, unsigned int inpu
        if (data->control_cpu < 0)
                return -ENXIO;
 
-       ret = rdmsrl_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap);
+       ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap);
        if (ret)
                return ret;
 
@@ -105,7 +105,7 @@ static int uncore_read_freq(struct uncore_data *data, unsigned int *freq)
        if (data->control_cpu < 0)
                return -ENXIO;
 
-       ret = rdmsrl_on_cpu(data->control_cpu, MSR_UNCORE_PERF_STATUS, &ratio);
+       ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_PERF_STATUS, &ratio);
        if (ret)
                return ret;