ufshcd_hold(hba, false);
        hba->clk_gating.is_suspended = true;
 
+       ufshcd_suspend_clkscaling(hba);
+
        if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
                        req_link_state == UIC_LINK_ACTIVE_STATE) {
                goto disable_clks;
 
        if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
            (req_link_state == hba->uic_link_state))
-               goto out;
+               goto enable_gating;
 
        /* UFS device & link must be active before we enter in this function */
        if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
                ret = -EINVAL;
-               goto out;
+               goto enable_gating;
        }
 
        if (ufshcd_is_runtime_pm(pm_op)) {
        ufshcd_vreg_set_lpm(hba);
 
 disable_clks:
-       /*
-        * The clock scaling needs access to controller registers. Hence, Wait
-        * for pending clock scaling work to be done before clocks are
-        * turned off.
-        */
-       ufshcd_suspend_clkscaling(hba);
-
        /*
         * Call vendor specific suspend callback. As these callbacks may access
         * vendor specific host controller register space call them before the
        if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
                ufshcd_disable_auto_bkops(hba);
 enable_gating:
+       ufshcd_resume_clkscaling(hba);
        hba->clk_gating.is_suspended = false;
        ufshcd_release(hba);
 out: