u8 *addrs, unsigned int *count)
{
u64 prov_id[SVC_I3C_MAX_DEVS] = {}, nacking_prov_id = 0;
- unsigned int dev_nb = 0, last_addr = 0, dyn_addr;
+ unsigned int dev_nb = 0, last_addr = 0, dyn_addr = 0;
u32 reg;
int ret, i;
* filling within a few hundred nanoseconds, which is significantly
* faster compared to the 64 SCL clock cycles.
*/
- dyn_addr = i3c_master_get_free_addr(&master->base, last_addr + 1);
- if (dyn_addr < 0)
- return -ENOSPC;
+ ret = i3c_master_get_free_addr(&master->base, last_addr + 1);
+ if (ret < 0)
+ break;
+ dyn_addr = ret;
writel(dyn_addr, master->regs + SVC_I3C_MWDATAB);
/*