drm/i915: relocate some DSPCNTR reg bit definitions

Some plane B/C specific bits were left next to the unused _DSPBCNTR
macro. Move them next to the DSPCNTR() macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/85409fbe5073797c0dc17df43eeb25abe9ff889f.1717773890.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index a2ba55fa2b30e0718a7bf1108a446a4bcdf36595..5d7ba824f35462cb7d37f93c8e09c0871b5099fc 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -38,10 +38,12 @@
 #define   DISP_STEREO_POLARITY_SECOND  REG_BIT(18)
 #define   DISP_ALPHA_PREMULTIPLY       REG_BIT(16) /* CHV pipe B */
 #define   DISP_ROTATE_180              REG_BIT(15) /* i965+ */
+#define   DISP_ALPHA_TRANS_ENABLE      REG_BIT(15) /* pre-g4x plane B */
 #define   DISP_TRICKLE_FEED_DISABLE    REG_BIT(14) /* g4x+ */
 #define   DISP_TILED                   REG_BIT(10) /* i965+ */
 #define   DISP_ASYNC_FLIP              REG_BIT(9) /* g4x+ */
 #define   DISP_MIRROR                  REG_BIT(8) /* CHV pipe B */
+#define   DISP_SPRITE_ABOVE_OVERLAY    REG_BIT(0) /* pre-g4x plane B/C */
 
 #define _DSPAADDR                              0x70184 /* pre-i965 */
 #define DSPADDR(dev_priv, plane)               _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df58cf38e14487512a6716f3f3e5fdc0e4dce7f8..4b05ce58b3a460ca07bb6add32e215ac43daa840 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2126,8 +2126,6 @@
 
 /* Display B control */
 #define _DSPBCNTR              (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
-#define   DISP_ALPHA_TRANS_ENABLE      REG_BIT(15)
-#define   DISP_SPRITE_ABOVE_OVERLAY    REG_BIT(0)
 #define _DSPBADDR              (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
 #define _DSPBSTRIDE            (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
 #define _DSPBPOS               (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)