Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
                return r;
 
        /* SDMA trap event */
-       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid,
                              SDMA3_5_0__SRCID__SDMA_TRAP,
                              &adev->sdma.trap_irq);
        if (r)
                        break;
                }
                break;
-       case SOC15_IH_CLIENTID_SDMA3:
+       case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
                switch (entry->ring_id) {
                case 0:
                        amdgpu_fence_process(&adev->sdma.instance[3].ring);
 
        SOC15_IH_CLIENTID_VCN1          = SOC15_IH_CLIENTID_UVD1,
        SOC15_IH_CLIENTID_SDMA2         = SOC15_IH_CLIENTID_ACP,
        SOC15_IH_CLIENTID_SDMA3         = SOC15_IH_CLIENTID_DCE,
+       SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid    = SOC15_IH_CLIENTID_ISP,
        SOC15_IH_CLIENTID_SDMA4         = SOC15_IH_CLIENTID_ISP,
        SOC15_IH_CLIENTID_SDMA5         = SOC15_IH_CLIENTID_VCE0,
        SOC15_IH_CLIENTID_SDMA6         = SOC15_IH_CLIENTID_XDMA,