struct drm_i915_private *i915 = to_i915(crtc->base.dev);
        struct intel_bw_state *bw_state =
                to_intel_bw_state(i915->display.bw.obj.state);
-       struct intel_dbuf_state *dbuf_state =
-               to_intel_dbuf_state(i915->display.dbuf.obj.state);
        struct intel_pmdemand_state *pmdemand_state =
                to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
        struct intel_crtc_state *crtc_state =
        intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains);
 
        intel_cdclk_crtc_disable_noatomic(crtc);
-
-       dbuf_state->active_pipes &= ~BIT(pipe);
+       skl_wm_crtc_disable_noatomic(crtc);
 
        bw_state->data_rate[pipe] = 0;
        bw_state->num_active_planes[pipe] = 0;
 
        skl_dbuf_sanitize(i915);
 }
 
+void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc)
+{
+       struct intel_display *display = to_intel_display(crtc);
+       struct intel_dbuf_state *dbuf_state =
+               to_intel_dbuf_state(display->dbuf.obj.state);
+       enum pipe pipe = crtc->pipe;
+
+       if (DISPLAY_VER(display) < 9)
+               return;
+
+       dbuf_state->active_pipes &= ~BIT(pipe);
+}
+
 void intel_wm_state_verify(struct intel_atomic_state *state,
                           struct intel_crtc *crtc)
 {
 
 void intel_wm_state_verify(struct intel_atomic_state *state,
                           struct intel_crtc *crtc);
 
+void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc);
+
 void skl_watermark_ipc_init(struct drm_i915_private *i915);
 void skl_watermark_ipc_update(struct drm_i915_private *i915);
 bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);