drm/amd/display: Revert "Improve x86 and dmub ips handshake"

This reverts commit 1288d702080949f87688d49dfeeacc99f40adc9b.

Causes intermittent hangs during reboot stress testing.

Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index f80917f6153b36ded3b2cace9a51d81ff2c5555d..302a3d348c76de1dce8d44323808d8fa1b8da7d5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -808,34 +808,6 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
        }
 }
 
-static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
-{
-       struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-       struct dc *dc = clk_mgr_base->ctx->dc;
-       uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
-
-       if (dc->config.disable_ips == 0) {
-               val |= DMUB_IPS1_ALLOW_MASK;
-               val |= DMUB_IPS2_ALLOW_MASK;
-       } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
-               val = val & ~DMUB_IPS1_ALLOW_MASK;
-               val = val & ~DMUB_IPS2_ALLOW_MASK;
-       } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
-               val |= DMUB_IPS1_ALLOW_MASK;
-               val = val & ~DMUB_IPS2_ALLOW_MASK;
-       } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
-               val |= DMUB_IPS1_ALLOW_MASK;
-               val |= DMUB_IPS2_ALLOW_MASK;
-       }
-
-       if (!allow_idle) {
-               val = val & ~DMUB_IPS1_ALLOW_MASK;
-               val = val & ~DMUB_IPS2_ALLOW_MASK;
-       }
-
-       dcn35_smu_write_ips_scratch(clk_mgr, val);
-}
-
 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
 {
        struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
@@ -855,13 +827,6 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
        return ips_supported;
 }
 
-static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)
-{
-       struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-
-       return dcn35_smu_read_ips_scratch(clk_mgr);
-}
-
 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
 {
        dcn35_init_clocks(clk_mgr);
@@ -949,8 +914,6 @@ static struct clk_mgr_funcs dcn35_funcs = {
        .set_low_power_state = dcn35_set_low_power_state,
        .exit_low_power_state = dcn35_exit_low_power_state,
        .is_ips_supported = dcn35_is_ips_supported,
-       .set_idle_state = dcn35_set_idle_state,
-       .get_idle_state = dcn35_get_idle_state
 };
 
 struct clk_mgr_funcs dcn35_fpga_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index b6b8c3ca1572ccf6097cc48539e868b121aae0cd..b20b3a5eb3c4755147622d280a1ea050d48ede85 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -444,9 +444,9 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *cl
                        enable);
 }
 
-int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
+void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
 {
-       return dcn35_smu_send_msg_with_param(
+       dcn35_smu_send_msg_with_param(
                clk_mgr,
                VBIOSSMC_MSG_DispPsrExit,
                0);
@@ -459,13 +459,3 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
                        VBIOSSMC_MSG_QueryIPS2Support,
                        0);
 }
-
-void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)
-{
-       REG_WRITE(MP1_SMN_C2PMSG_71, param);
-}
-
-uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
-{
-       return REG_READ(MP1_SMN_C2PMSG_71);
-}

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
index 2b8e6959a03d001fba3e0cc9ec65778b0f589bda..38b7a4420d6ce72cb771385fc9433be0144774c1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
@@ -194,10 +194,8 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst
 void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
 void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
 
-int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
+void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
 int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);
 int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);
 int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);
-void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param);
-uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr);
 #endif /* DAL_DC_35_SMU_H_ */

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 582d94c759f656375792540b0d68ecf048818029..342022b7ab37ec969eb1f4b3f22390649890a6c7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -975,8 +975,6 @@ struct dc_debug_options {
        bool replay_skip_crtc_disabled;
        bool ignore_pg;/*do nothing, let pmfw control it*/
        bool psp_disabled_wa;
-       unsigned int ips2_eval_delay_us;
-       unsigned int ips2_entry_delay_us;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 4fd3f09432be4fe92a4ee1336eca4144a21e4c2e..a388f34c6d04e129fb5685983e63690b60486873 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1100,64 +1100,31 @@ void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
 
        cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
 
-       if (allow_idle) {
-               if (dc->hwss.set_idle_state)
-                       dc->hwss.set_idle_state(dc, true);
-       }
-
        dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
+
+       if (allow_idle)
+               udelay(500);
 }
 
 void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
 {
-       uint32_t allow_state = 0;
-       uint32_t commit_state = 0;
-
        if (dc->debug.dmcub_emulation)
                return;
 
        if (!dc->idle_optimizations_allowed)
                return;
 
-       if (dc->hwss.get_idle_state &&
-               dc->hwss.set_idle_state &&
-               dc->clk_mgr->funcs->exit_low_power_state) {
-
-               allow_state = dc->hwss.get_idle_state(dc);
-               dc->hwss.set_idle_state(dc, false);
-
-               if (allow_state & DMUB_IPS2_ALLOW_MASK) {
-                       // Wait for evaluation time
-                       udelay(dc->debug.ips2_eval_delay_us);
-                       commit_state = dc->hwss.get_idle_state(dc);
-                       if (commit_state & DMUB_IPS2_COMMIT_MASK) {
-                               // Tell PMFW to exit low power state
-                               dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
-
-                               // Wait for IPS2 entry upper bound
-                               udelay(dc->debug.ips2_entry_delay_us);
-                               dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
+       // Tell PMFW to exit low power state
+       if (dc->clk_mgr->funcs->exit_low_power_state)
+               dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
 
-                               do {
-                                       commit_state = dc->hwss.get_idle_state(dc);
-                               } while (commit_state & DMUB_IPS2_COMMIT_MASK);
+       // Wait for dmcub to load up
+       dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
 
-                               if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
-                                       ASSERT(0);
-
-                               return;
-                       }
-               }
-
-               dc_dmub_srv_notify_idle(dc, false);
-               if (allow_state & DMUB_IPS1_ALLOW_MASK) {
-                       do {
-                               commit_state = dc->hwss.get_idle_state(dc);
-                       } while (commit_state & DMUB_IPS1_COMMIT_MASK);
-               }
-       }
+       // Notify dmcub disallow idle
+       dc_dmub_srv_notify_idle(dc, false);
 
-       if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
-               ASSERT(0);
+       // Confirm dmu is powered up
+       dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c
index 296bf3a38cb906b10a1b0c36cfec41419a141d08..3ccf1c8cedda7fd78a9cf939dac59e14d390270d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c
@@ -120,8 +120,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
        .calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
        .block_power_control = dcn35_block_power_control,
        .root_clock_control = dcn35_root_clock_control,
-       .set_idle_state = dcn35_set_idle_state,
-       .get_idle_state = dcn35_get_idle_state
 };
 
 static const struct hwseq_private_funcs dcn35_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 3edc57acab78e3bea51746b515a292f797ec0446..f9166c1a6a3408c0f7bc369bba6e629aa65f2998 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -748,8 +748,6 @@ static const struct dc_debug_options debug_defaults_drv = {
        .disable_z10 = false,
        .ignore_pg = true,
        .psp_disabled_wa = true,
-       .ips2_eval_delay_us = 200,
-       .ips2_entry_delay_us = 400
 };
 
 static const struct dc_panel_config panel_config_defaults = {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index d3429134b2e3227ee18fc111fb0aa9851eb00c19..8f717db01f8537059757f0db2064a4af3a248171 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -652,10 +652,18 @@ bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)
 
        // TODO: review other cases when idle optimization is allowed
 
+       if (!enable) {
+               // Tell PMFW to exit low power state
+               if (dc->clk_mgr->funcs->exit_low_power_state)
+                       dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
+
+               dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
+       }
+
+       dc_dmub_srv_notify_idle(dc, enable);
+
        if (!enable)
-               dc_dmub_srv_exit_low_power_state(dc);
-       else
-               dc_dmub_srv_notify_idle(dc, enable);
+               dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
 
        return true;
 }
@@ -1189,19 +1197,3 @@ void dcn35_optimize_bandwidth(
                        dc->hwss.root_clock_control(dc, &pg_update_state, false);
        }
 }
-
-void dcn35_set_idle_state(const struct dc *dc, bool allow_idle)
-{
-       // TODO: Find a more suitable communcation
-       if (dc->clk_mgr->funcs->set_idle_state)
-               dc->clk_mgr->funcs->set_idle_state(dc->clk_mgr, allow_idle);
-}
-
-uint32_t dcn35_get_idle_state(const struct dc *dc)
-{
-       // TODO: Find a more suitable communcation
-       if (dc->clk_mgr->funcs->get_idle_state)
-               return dc->clk_mgr->funcs->get_idle_state(dc->clk_mgr);
-
-       return 0;
-}

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index 0dff10d179b86d0d82ed58ac6e9b2febe018f916..9b66ab0c909cd3c78ee81c8b64e27a0034b15793 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -81,7 +81,4 @@ void dcn35_dsc_pg_control(
                struct dce_hwseq *hws,
                unsigned int dsc_inst,
                bool power_on);
-
-void dcn35_set_idle_state(const struct dc *dc, bool allow_idle);
-uint32_t dcn35_get_idle_state(const struct dc *dc);
 #endif /* __DC_HWSS_DCN35_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 452680fe9aabd557b8cdc06e0c4a8b81224cdcef..d45302035e3fe44aebacd01507f77b36ec25ab7b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -418,8 +418,7 @@ struct hw_sequencer_funcs {
                struct pg_block_update *update_state, bool power_on);
        void (*root_clock_control)(struct dc *dc,
                struct pg_block_update *update_state, bool power_on);
-       void (*set_idle_state)(const struct dc *dc, bool allow_idle);
-       uint32_t (*get_idle_state)(const struct dc *dc);
+
        bool (*is_pipe_topology_transition_seamless)(struct dc *dc,
                        const struct dc_state *cur_ctx,
                        const struct dc_state *new_ctx);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index fa9614bcb1605f6b75f116ca5387df338bc3dc4c..cb2dc3f75ae2888cb1807599ea8fae767750b29c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -262,8 +262,6 @@ struct clk_mgr_funcs {
        void (*set_low_power_state)(struct clk_mgr *clk_mgr);
        void (*exit_low_power_state)(struct clk_mgr *clk_mgr);
        bool (*is_ips_supported)(struct clk_mgr *clk_mgr);
-       void (*set_idle_state)(struct clk_mgr *clk_mgr, bool allow_idle);
-       uint32_t (*get_idle_state)(struct clk_mgr *clk_mgr);
 
        void (*init_clocks)(struct clk_mgr *clk_mgr);