dev_warn(host->dev,
                        "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
                nand_chip->ecc.mode = NAND_ECC_SOFT;
+               nand_chip->ecc.algo = NAND_ECC_HAMMING;
                return 0;
        }
 
                /* page size not handled by HW ECC */
                /* switching back to soft ECC */
                nand_chip->ecc.mode = NAND_ECC_SOFT;
+               nand_chip->ecc.algo = NAND_ECC_HAMMING;
                return 0;
        }
 
         * even if the nand-ecc-mode property is not defined.
         */
        host->nand_chip.ecc.mode = NAND_ECC_SOFT;
+       host->nand_chip.ecc.algo = NAND_ECC_HAMMING;
 
        return 0;
 }
                dev_err(host->dev,
                        "Can't get I/O resource regs, use software ECC\n");
                nand_chip->ecc.mode = NAND_ECC_SOFT;
+               nand_chip->ecc.algo = NAND_ECC_HAMMING;
                return 0;
        }
 
                /* page size not handled by HW ECC */
                /* switching back to soft ECC */
                nand_chip->ecc.mode = NAND_ECC_SOFT;
+               nand_chip->ecc.algo = NAND_ECC_HAMMING;
                return 0;
        }
 
                       sizeof(struct atmel_nand_data));
                nand_chip->ecc.mode = host->board.ecc_mode;
 
+               /*
+                * When using software ECC every supported avr32 board means
+                * Hamming algorithm. If that ever changes we'll need to add
+                * ecc_algo field to the struct atmel_nand_data.
+                */
+               if (nand_chip->ecc.mode == NAND_ECC_SOFT)
+                       nand_chip->ecc.algo = NAND_ECC_HAMMING;
+
                /* 16-bit bus width */
                if (host->board.bus_width_16)
                        nand_chip->options |= NAND_BUSWIDTH_16;