drm/amd/display: Use DCC meta pitch for MALL allocation requirements

[Description]
Calculations for determining DCC meta size should be pitch*height*bpp/256.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 76548b4b822c21423cae2003031f6f37349bc17d..c9b2343947beaaeff75b1803c47afd4d4022772a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -262,11 +262,11 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c
                num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *
                                ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);
 
-               /* For DCC:
-                * meta_num_mblk = CEILING(full_mblk_width_ub_l*full_mblk_height_ub_l*Bpe/256/mblk_bytes, 1)
+               /*For DCC:
+                * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1)
                 */
                if (pipe->plane_state->dcc.enable)
-                       num_mblks += (mall_alloc_width_blk_aligned * mall_alloc_width_blk_aligned * bytes_per_pixel +
+                       num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel +
                                        (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES);
 
                bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index d869c057230f0751075d86dcb54bf5852e0c1bd8..783935c4e6644cef21755fff6f7d1412cac7eff4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -121,14 +121,19 @@ uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc *dc, struct dc_stat
                         */
                        num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *
                                        ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);
+
+                       /*For DCC:
+                        * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1)
+                        */
+                       if (pipe->plane_state->dcc.enable)
+                               num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel +
+                                                               (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES);
+
                        bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;
                        // cache lines used is total bytes / cache_line size. Add +2 for worst case alignment
                        // (MALL is 64-byte aligned)
                        cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2;
 
-                       /* For DCC divide by 256 */
-                       if (pipe->plane_state->dcc.enable)
-                               cache_lines_per_plane = cache_lines_per_plane + (cache_lines_per_plane / 256) + 1;
                        cache_lines_used += cache_lines_per_plane;
                }
        }