drm/i915/gtt: Split out i915_gem_gtt_rebind_object()

... in preparation for changing the cache level (and thus the flags upon
the PTEs) dynamically.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e46b645773cfcb7ca65352996d49761a8cf7872f..837033cf2ce5ef3181d3246ba2d5804670071a8f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -29,6 +29,9 @@
 #include "i915_trace.h"
 #include "intel_drv.h"
 
+static void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
+                                      enum i915_cache_level cache_level);
+
 /* XXX kill agp_type! */
 static unsigned int cache_level_to_agp_type(struct drm_device *dev,
                                            enum i915_cache_level cache_level)
@@ -59,24 +62,8 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
                              (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
 
        list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
-               unsigned int agp_type =
-                       cache_level_to_agp_type(dev, obj->cache_level);
-
                i915_gem_clflush_object(obj);
-
-               if (dev_priv->mm.gtt->needs_dmar) {
-                       BUG_ON(!obj->sg_list);
-
-                       intel_gtt_insert_sg_entries(obj->sg_list,
-                                                   obj->num_sg,
-                                                   obj->gtt_space->start >> PAGE_SHIFT,
-                                                   agp_type);
-               } else
-                       intel_gtt_insert_pages(obj->gtt_space->start
-                                                  >> PAGE_SHIFT,
-                                              obj->base.size >> PAGE_SHIFT,
-                                              obj->pages,
-                                              agp_type);
+               i915_gem_gtt_rebind_object(obj, obj->cache_level);
        }
 
        intel_gtt_chipset_flush();
@@ -110,6 +97,27 @@ int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
        return 0;
 }
 
+static void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
+                                      enum i915_cache_level cache_level)
+{
+       struct drm_device *dev = obj->base.dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);
+
+       if (dev_priv->mm.gtt->needs_dmar) {
+               BUG_ON(!obj->sg_list);
+
+               intel_gtt_insert_sg_entries(obj->sg_list,
+                                           obj->num_sg,
+                                           obj->gtt_space->start >> PAGE_SHIFT,
+                                           agp_type);
+       } else
+               intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
+                                      obj->base.size >> PAGE_SHIFT,
+                                      obj->pages,
+                                      agp_type);
+}
+
 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 {
        intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,