clk: rockchip: rk3368: fix edp_24m parent

The edp_24m parent select bit define is:
1'b0:xin24m
1'b1:1'b0(dummy)
so adapt the parent sel bit to the currect one.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 7016ed24bbe5dc311a245b1cfc0efd10d1a0878e..dab759b2d18c41d92fd2676aec0099a55931004d 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -121,7 +121,7 @@ PNAME(mux_i2s_2ch_p)                = { "i2s_2ch_src", "i2s_2ch_frac",
                                    "dummy", "xin12m" };
 PNAME(mux_spdif_8ch_p)         = { "spdif_8ch_pre", "spdif_8ch_frac",
                                    "ext_i2s", "xin12m" };
-PNAME(mux_edp_24m_p)           = { "dummy", "xin24m" };
+PNAME(mux_edp_24m_p)           = { "xin24m", "dummy" };
 PNAME(mux_vip_out_p)           = { "vip_src", "xin24m" };
 PNAME(mux_usbphy480m_p)                = { "usbotg_out", "xin24m" };
 PNAME(mux_hsic_usbphy480m_p)   = { "usbotg_out", "dummy" };